Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

Mohapatra, Sushanta Kumar; Pradhan, K P; Artola, L.; Sahu, Prasanna Kumar

doi:10.1016/j.mssp.2014.12.026

Cited by 91 publications

(23 citation statements)

References 32 publications

(31 reference statements)

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…So, it is essential to simulate for studying performance variation in view of analog and RF circuit application. In continuation with our previous reported article on DG-MOSFET [20], [21], a unique attempt has been made to present deep analysis of process variability dependency on various performance metrics of 3D FinFET. This paper is organized in different sections.…”

Section: Introductionmentioning

confidence: 99%

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Mohapatra¹,

Pradhan²,

Singh³

et al. 2015

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

Now a days FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This work studies the impact of HFin and WFin variations on various performance matrices including static as well dynamic figures of merit (FOMs). With the help of Aspect Ratio (WFin/HFin). The device is branched into three parts i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the DC as well as AC figures of merit (FOMs). The static or low frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF=gm/ID), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this report can be of great help to device engineers in designing 3-D devices as per their requirement.A 1536-125X (c)

show abstract

Section: Introductionmentioning

confidence: 99%

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Mohapatra¹,

Pradhan²,

Singh³

et al. 2015

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

show abstract

“…3(a) and (b) represents the I D -V GS (log scale) and g m -V GS characteristics respectively. I off is maintained at nearly constant value of both device cases at V DS = 0.1 V, for a better comparison in analog/RF performances [22], which can be observed from the inset figure of Fig. 3(a) and it is in the range between 10 À10 A/lm and 10 À11 A/lm.…”

Section: Performance Measure Of Doping Less Dmgo-sgoimentioning

confidence: 87%

Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

Pradhan

Sahu

Singh

et al. 2015

Superlattices and Microstructures

Self Cite

View full text Add to dashboard Cite

“…Transconductance generation factor TGF [21] is an analog performance parameter estimated by the equation 6where is the transconductance of the device.…”

Section: ⃗⃗⃗ ⃗⃗⃗⃗mentioning

confidence: 99%

A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control

Mangesh¹,

Chopra²,

Krishan³

2019

ijacsa

View full text Add to dashboard Cite

An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal crosssection FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.

show abstract

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

Cited by 91 publications

References 32 publications

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control

Contact Info

Product

Resources

About