The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Abstract

Now a days FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This work studies the impact of HFin and WFin variations on various performance matrices including static as well dynamic figures of merit (FOMs). With the help of Aspect Ratio (WFin/HFin). The device is branched into three parts i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the DC as well as AC figures of merit (FOMs). The static or low frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF=gm/ID), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this report can be of great help to device engineers in designing 3-D devices as per their requirement.A 1536-125X (c)

Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

“…The principal idea of this work is to create symmetric underlap regions at both S/D side of the hybrid FinFET and pattern the regions with high-k dielectric spacer material (HfO 2 , k ¼ 22) and compare it with conventional FinFET having low-k spacer oxide (Si 3 N 4 ) [15]. The electrical and physical parameters are calibrated to meet the ITRS specifications for 14-nm physical gate length [3,15].…”

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

“…And the transistor which has multiple fins increases the parasitic resistance (from each fin) and adds interconnect capacitances between fins [24] [25]. Also, the fabrication process is complicated and more complex than planar technologies especially for the vertical etching, which gives more opportunities to have variations between the shapes and heights of the Fins [26] which causes a variation of the threshold voltage of each transistor [27] as shown in Figure 21.…”

Variability of FinFET AC parameters: A physics‐based insight

“…Despite the enormous amount of work dedicated to the fabrication, optimization, and modeling of these devices, comparably less effort has been dedicated to their AC characterization and modeling, although the interest towards analog Radio Frequency (RF) and microwave applications fosters research in this field. On the other hand, the peculiar 3D device structure brings along a considerable amount of parasitic capacitances and resistances,() which may impair, in RF applications, the advantages brought by the gate length reduction. Since variability is known to significantly impact the DC device behavior, the same is expected for AC performance, both at the active device and at the parasitics level.…”