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Abstract-A robust genetic circuit optimizer using Unscented Transform and Non-dominated Sorting Genetic Algorithm-II is presented. The algorithm provides significant decrease in computational cost compared to Monte Carlo method. This transform permits the circuit performance uncertainties determination from components uncertainties, thus, a search through robustness can be done. Results shows reduced computational costs, the many possibilities provided to circuit designer by the multi-objective search and assumptions that can be done in a Doherty power amplifier study with the optimizer.

A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the splitter, the combiner and the DC bias feed to partition the power requirements among the parallelised power cells. An individual cell can be dynamically turned ON/OFF according to the desired output power. At 2.5 GHz, the measured maximum output power is 28.2 dBm and the power-added efficiency is improved for low level, +3.2 and +4.9% for 18 and 23.7 dBm, respectively.Introduction: Modern wireless communication applications, such as fast Internet, video streaming and so on, are governed by different standards and specifications but have at least one common point, i.e. high data rates, and so high linearity requirements. Furthermore, reducing power consumption becomes a major issue in handset wireless transceivers. In these transceivers, special care had to be taken regarding the efficiency of power amplifiers (PAs). Usually, PAs present maximum efficiency at the maximum output power required by the standard of communication used. For lower levels, in the linear region, the efficiency falls dramatically. As recent standards used signals with high peak to average power ratios (PAPRs), handsets transmit at lower and medium level most of the time. This leads to a low mean efficiency. To overcome this issue, several techniques have been studied in the literature. The first category consists in dynamically reconfiguring the PA, by controlling the quiescent current and/or the supply voltage [1], the number of PAs in parallel [2] or by using the envelope tracking structure [3]. The second category controls the load seen by the PA with a Doherty structure [4] or harmonic control [5]. In this Letter, a CMOS fully integrated PA based on a power cell switching (PCS) structure is implemented in a 65 nm CMOS technology. Compared with other techniques, the proposed structure allows dealing with large bandwidth signals and enables the PA to be power-controlled. Hence, the proposed PA is able to provide enhanced average efficiency, whatever the input power level.

in this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The new transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two times less than a fully analog system.

A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. The amplifier has 23.4 dBm output power and both PAE peaks have the same level in 25%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce losses and correctly balance their behavior.I.

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In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA Zero-Intermediate Frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator and a digital stage adjusting the phase rotation around the loop. The digital phase-alignment system consumes 2.94 mW (tree time less than a full-analog system).