In this paper, a trajectory tracking control for a nonholonomic mobile robot subjected to kinematic disturbances is proposed. A variable structure controller based on the sliding mode theory is designed, and applied to compensate these disturbances. To minimize the problems found in practical implementations of the classical variable structure controllers, and eliminate the chattering phenomenon, is used a neural compensator, which is nonlinear and continuous, in lieu of the discontinuous portion of the control signals present in classical forms. This proposed neural compensator is designed by the Gaussian radial basis function neural networks modeling technique and it does not require the time-consuming training process. Stability analysis is guaranteed based on the Lyapunov method. Simulation results are provided to show the effectiveness of the proposed approach.
Abstract-A robust genetic circuit optimizer using Unscented Transform and Non-dominated Sorting Genetic Algorithm-II is presented. The algorithm provides significant decrease in computational cost compared to Monte Carlo method. This transform permits the circuit performance uncertainties determination from components uncertainties, thus, a search through robustness can be done. Results shows reduced computational costs, the many possibilities provided to circuit designer by the multi-objective search and assumptions that can be done in a Doherty power amplifier study with the optimizer.
This paper describes the synthesis method and implementation in 65-nm CMOS technology of a compact analog phase-shifter (PS) dedicated to 24/28 GHz applications. This PS delivers a phase shift continuously tunable from 0 to 55° and is particularly suited for on-chip or in-package phased-array antenna. The proposed topology, which is based on an all-pass circuit that includes coupled microstrip lines and varactors as tunable components is intrinsically compact and shows an interesting phase-range vs capacitance-variation ratio.
A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. The amplifier has 23.4 dBm output power and both PAE peaks have the same level in 25%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce losses and correctly balance their behavior.I.
This paper deals with the implementation of a RF Doherty Power Amplifier (DPA) with the objective of improving the average efficiency. This technique is an interesting way to provide efficient PA for high PAPR signal of more recent standards of communications. The Doherty principle is applied to a 2.5GHz fully integrated PA on a CMOS 65nm technology. The DPA exhibits 23.4dBm output power, 15dB of power gain and 24.7% of PAE on a 7 dB power range. The die size is 2.89mm2. To fulfill high data rates, wide-band behavior is a big challenge. Hence the wideband behavior of integrated DPA is also investigated.Index Terms -RF CMOS integrated circuit, Doherty power amplifier, efficiency enhancement.
Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P out in 2dB.
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