Fully integrated CMOS Doherty Power Amplifier with network matching optimization for die size reduction

Abstract

Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P out in 2dB.

Asymmetric Doherty Power Amplifier with Input Phase/Power Adjustment and Envelope Tracking

“…Plan A Plan B Many works on DPAs have been carried out recently for both miniature and high frequencies. MMICs in GaAs, GaN, and CMOS processing are proposed in the recent literatures [27][28][29][30][31], which also show good performances by using some compact matching techniques.…”

Integrated Doherty RF CMOS Power Amplifier design for average efficiency enhancement

“…These functions are realized with localized elements, capacitors and inductors. An important optimization work has to be done on the DPA topology to decrease the number of passives components [11]. The die photograph is shown in Figure 5.…”

“…The low quality factor of passive components on CMOS 65nm bulk technology helps getting high 3-dB bandwidth. Moreover, to save die area, topology optimization was done and described in [11]. Figure 7 presents measured results in an 8.8dB range of output power (from 14.6dBm to 23.4dBm) in 2.2-2.8 GHz band.…”