Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

Cheng, Kangguo; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Haran, Bala; Kumar, Amitesh; Adam, Thomas; Reznicek, A.; Loubet, N.; He, Hau; Kuss, J.; Wang, M.; Levin, T. M.; Monsieur, F.; Liu, Q.; Sreenivasan, R.; Cai, Jin; Kimball, A. S.; Mehta, S.; Luning, S.; Zhu, Yuxuan; Zhu, Zhengmao; Yamamoto, Tetsuya; Bryant, A.; Lin, CL; Naczas, Sebastian; Jagannathan, H.; Edge, L. F.; Allegret-Maret, S.; Dube, Abhishek; Kanakasabapathy, S.; Schmitz, Stefan; Inada, A.; Seo, Sang Soo; Raymond, M.; Zhang, Z.; Yagishita, Akira; Demarest, J.; Li, J.; Hopstaken, M.; Berliner, N.; Upham, A.; Johnson, Rob; Holmes, Steven J.; Standaert, T.; Smalley, M.; Zamdmer, N.; Ren, Zhibin; Nagumo, T.; Wu, Tan Mau; Bu, Hanyoung; Paruchuri, Vamsi; Sadana, D. K.; Narayanan, V.; Haensch, Wilfried; O'Neill, J.; Hook, T.; Khare, Mukesh; Shahidi, G.; Doris, B.

doi:10.7567/ssdm.2011.d-7-1

Cited by 4 publications

(2 citation statements)

References 1 publication

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“…A faceted SEG in S/D has been shown to reduce R S=D and minimize gate-to-S/D parasitic capacitance. 13,19) Its impact on the lateral electric field for a L gate $ 70 nm device under the biasing conditions corresponding to the hold ''0'' state (V G ¼ À2:5 V, V B ¼ 2:5 V and V S ¼ V D ¼ 0 V) is shown in Fig. 14.…”

Section: Device Results and Discussionmentioning

confidence: 99%

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Veloso¹,

Keersgieter²,

Aoulaiche³

et al. 2013

Jpn. J. Appl. Phys.

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In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I OFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I ON/I OFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.

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Section: Device Results and Discussionmentioning

confidence: 99%

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Veloso¹,

Keersgieter²,

Aoulaiche³

et al. 2013

Jpn. J. Appl. Phys.

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“…State-of-the-art on-insulator-based MISFETs such as an ultrathin-body (UTB) low doped Si-on-insulator (SOI) MISFET is a typical example that exhibits high carrier mobility and steep subthreshold slope. 1,2) Further enhancement of such performance has been proposed considering several approaches. One is the introduction of channel materials with a higher carrier mobility than that of Si-channel MISFETs to increase the drive current under the same supply voltage conditions.…”

mentioning

confidence: 99%

Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al₂O₃/SiO₂hybrid buried oxide layers

Moriyama

Ikeda

Takeuchi

et al. 2014

Appl. Phys. Express

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An ultrathin-body Ge-on-insulator (GeOI) wafer having a bonded thin Al2O3/SiO2 hybrid buried oxide layer was fabricated using an epitaxially grown Ge film on Si as a Ge donor layer. The epitaxial Ge film was confirmed to have a negligibly low density of crystal-defect-induced p-type carriers and was successfully transferred to form the GeOI wafer. Strong Al2O3/SiO2 bonding effectively suppressed Ge exfoliation during the wafering process. The obtained device-grade GeOI layer and strong bonding strength between Al2O3 and SiO2 are potentially advantageous for future Si-based complementary metal–insulator–semiconductor (CMIS) fabrication processes utilizing large-diameter Si wafers.

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Highly sensitive and functional photodetectors based on silicon-on-insulator

Inokawa

Satoh

Ueta

2016

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

Cited by 4 publications

References 1 publication

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al₂O₃/SiO₂hybrid buried oxide layers

Highly sensitive and functional photodetectors based on silicon-on-insulator

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Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

Cited by 4 publications

References 1 publication

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al2O3/SiO2hybrid buried oxide layers

Highly sensitive and functional photodetectors based on silicon-on-insulator

Contact Info

Product

Resources

About

Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al₂O₃/SiO₂hybrid buried oxide layers