Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al2O3/SiO2hybrid buried oxide layers

Moriyama, Yoshihiko; Ikeda, Keiji; Takeuchi, Shinichi; Kamimuta, Yuuichi; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira; Tezuka, T.

doi:10.7567/apex.7.086501

Cited by 20 publications

(15 citation statements)

References 20 publications

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“…Many crystal growth methods in the semiconductor industry rely on Si and its interface with silica because of remarkable synergy between Si and silica (a-SiO 2 ). − Therefore, several studies have attempted to gain deeper insight into the formation of the a-SiO 2 /Si interface which is accomplished by oxygen diffusion process during Si oxidation. − Under the thermal treatment of the interface, an O atom moves through the silica network by leaving a vacancy behind and reacts with Si–Si bond in the vicinity of the interface. The O atom residing in Si–Si bond-centered (BC) site continues to diffuse along a path comprising a combination of O jumps between BC sites in the Si substrate. − During the jump, the O atom goes through transition state by overcoming the diffusion barrier of 2.53 eV. , Recent density functional theory (DFT) studies , showed the dependence of the energy barrier on the geometrical description of the transition state.…”

Section: Introductionmentioning

confidence: 99%

Development of the ReaxFF Reactive Force Field for Inherent Point Defects in the Si/Silica System

2019

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We redeveloped the ReaxFF force field parameters for Si/O/H interactions that enable molecular dynamics (MD) simulations of Si/SiO2 interfaces and O diffusion in bulk Si at high temperatures, in particular with respect to point defect stability and migration. Our calculations show that the new force field framework (ReaxFFpresent), which was guided by the extensive quantum mechanical-based training set, describes correctly the underlying mechanism of the O-migration in Si network, namely, the diffusion of O in bulk Si occurs by jumping between the neighboring bond-centered sites along a path in the (110) plane, and during the jumping, O goes through the asymmetric transition state at a saddle point. Additionally, the ReaxFFpresent predicts the diffusion barrier of O-interstitial in the bulk Si of 64.8 kcal/mol, showing a good agreement with the experimental and density functional theory values in the literature. The new force field description was further applied to MD simulations addressing O diffusion in bulk Si at different target temperatures ranging between 800 and 2400 K. According to our results, O diffusion initiates at the temperatures over 1400 K, and the atom diffuses only between the bond-centered sites even at high temperatures. In addition, the diffusion coefficient of O in Si matrix as a function of temperature is in overall good agreement with experimental results. As a further step of the force field validation, we also prepared amorphous SiO2 (a-SiO2) with a mass density of 2.21 gr/cm3, which excellently agrees with the experimental value of 2.20 gr/cm3, to model a-SiO2/Si system. After annealing the a-SiO2/Si system at high temperatures until below the computed melting point of bulk Si, the results show that ReaxFFpresent successfully reproduces the experimentally and theoretically defined diffusion mechanism in the system and succeeded in overcoming the diffusion problem observed with ReaxFFSiOH(2010), which results in O diffusion in the Si substrate even at the low temperature such as 300 K.

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Section: Introductionmentioning

confidence: 99%

Development of the ReaxFF Reactive Force Field for Inherent Point Defects in the Si/Silica System

2019

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“…Then, Al 2 O 3 /Ge and SiO 2 /Si were manually bonded in a cleanroom environment. After annealing in N 2 ambient at 300 °C to enhance bonding strength, 28) layer splitting was carried out by annealing at 400 °C. Ge thickness after layer splitting measured by an atomic force microscope (AFM) was 876 nm, which is close to the peak depth of the implanted H + from the original Ge surface.…”

Section: Experimental Methodsmentioning

confidence: 99%

Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator: Schottky tunneling source mode operation and conventional mode operation

Yamamoto

Nakae

Wang

et al. 2019

Jpn. J. Appl. Phys.

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An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.

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“…78) It should be noted here that Ge channels thinner than 20 or 10 nm are strongly needed in advanced logic devices, irrespective of planar structure such as fully-depleted SOI or vertical Fin structures, to realize high immunity against the short-channel effects, which is one of the most difficult challenges in scaled MOSFETs. There are many ways 78,79) to form Ge layers on Si or GOI structures, such as selective epitaxy of Ge films on Si, 80,81) smart-cut GOI wafers, [82][83][84] direct wafer bonding, 79,[85][86][87][88][89] Ge condensation, [89][90][91][92] the lateral overgrowth of Ge films on insulators, 93,94) and direct epitaxy of Ge films on crystal oxides. 95,96) Among them, ultrathin body GOI structures formed by the Ge condensation technique [89][90][91][92] are promising for the advanced CMOS logic devices.…”

Section: Ge Channel Formation On Simentioning

confidence: 99%

III–V/Ge channel MOS device technologies in nano CMOS era

Takagi

Zhang

Suh

et al. 2015

Jpn. J. Appl. Phys.

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CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.

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Ultrathin-body Ge-on-insulator wafers fabricated with strongly bonded thin Al₂O₃/SiO₂hybrid buried oxide layers

Cited by 20 publications

References 20 publications

Development of the ReaxFF Reactive Force Field for Inherent Point Defects in the Si/Silica System

Development of the ReaxFF Reactive Force Field for Inherent Point Defects in the Si/Silica System

Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator: Schottky tunneling source mode operation and conventional mode operation

III–V/Ge channel MOS device technologies in nano CMOS era

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