Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers

Abstract

Electronic structures and the phonon-limited electron mobility of inversion layers have been studied at 300 K for the thin Si (100) layer of double-gate (DG) silicon-on-insulator (SOI) structures by using a one-dimensional self-consistent calculation and a relaxation time approximation. Both symmetric and asymmetric DG SOI systems have been investigated. The self-consistent calculation presents the electronic structures specific to DG SOI Si inversion layers and the range of the specific electronic structures as functions of Si layer thickness tSi and the vertical effective electric field Eeff. Outside this range, the mobility behavior as a function of Eeff is almost identical to that of bulk Si inversion layers. In this range, however, as tSi decreases, the phonon-limited electron mobility μph increases gradually to a maximum around tSi=10 nm, decreases for tSi=10–5 nm, rises rapidly to another maximum in the vicinity of tSi=3 nm and finally falls. The former gradual increase in the mobility μph results from a reduction of phonon scattering caused by the interaction of upper and lower inversion layers. For tSi of less than approximately 10 nm, the mobility of each subband is reduced by an enhancement of scattering rates due to a confinement effect in general. However, the rapid increase of the fraction of electrons in the lowest energy subband that has a higher mobility than other subbands brings about the latter mobility increase in the vicinity of tSi=3 nm.

Monte Carlo simulation of nanoelectronic devices

“…Figure 6 shows the electron mobility versus silicon layer thickness for two different electric field values. Basically, our Monte Carlo results reproduce, qualitatively, the results obtained by Shoji et al [19] for DGSOI inversion layers using the relaxation time approximation. As silicon thickness is reduced, the phonon-limited mobility increases gradually to a maximum around T w = 10 nm (for E EFF = 5 × 10 5 V/cm), decreases in the T w = 5-10 nm range to values below those of this parameter in conventional bulk MOSFETs, rises rapidly to another maximum in the vicinity of T w = 3 nm and finally falls.…”

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

“…For comparison, it was found that the effective field in undoped double gate channel is 0.5 MV/ cm which is half of that in a normal bulk MOSFET [30]. However, even with lightly doped or undoped channel, the electron mobility degradation for channel thickness below 20 nm may be clearly observed at a low inversion carrier density (10 12 cm À2 ), due to phonon scattering in the thin confined channel [31].…”

Optimization of saddle junctionless FETs for extreme high integration

“…A standard band-to-band tunneling (BTBT) model is also selected to simulate the effect of device leakage current. It should be declared that a numerical analysis of quantum effect verifies that the classical simulation is valid for the scale of silicon larger than 5 nm [18], and thereafter the quantum confinement has been neglected during the whole simulations. The simulation parameters of the saddle-gate JL FETs with high-k gate dielectric are listed in Table 1.…”