Electronic structures and the phonon-limited electron mobility of inversion layers have been studied at 300 K for the thin Si (100) layer of double-gate (DG) silicon-on-insulator (SOI) structures by using a one-dimensional self-consistent calculation and a relaxation time approximation. Both symmetric and asymmetric DG SOI systems have been investigated. The self-consistent calculation presents the electronic structures specific to DG SOI Si inversion layers and the range of the specific electronic structures as functions of Si layer thickness tSi and the vertical effective electric field Eeff. Outside this range, the mobility behavior as a function of Eeff is almost identical to that of bulk Si inversion layers. In this range, however, as tSi decreases, the phonon-limited electron mobility μph increases gradually to a maximum around tSi=10 nm, decreases for tSi=10–5 nm, rises rapidly to another maximum in the vicinity of tSi=3 nm and finally falls. The former gradual increase in the mobility μph results from a reduction of phonon scattering caused by the interaction of upper and lower inversion layers. For tSi of less than approximately 10 nm, the mobility of each subband is reduced by an enhancement of scattering rates due to a confinement effect in general. However, the rapid increase of the fraction of electrons in the lowest energy subband that has a higher mobility than other subbands brings about the latter mobility increase in the vicinity of tSi=3 nm.

Phonon-limited inversion layer electron mobility in extremely thin (100) Si layers of silicon-on-insulator field-effect transistors has been studied at 300 K using a relaxation time approximation and a one-dimensional self-consistent calculation. For the Si layer thickness tSi of more than approximately 5 nm, the mobility behavior as a function of an effective vertical electric field is found to be almost identical with that of bulk Si inversion layers. For a thickness of less than that, however, the mobility behavior is considerably affected by the change in the electronic structures due to a confinement effect. As the Si layer thickness decreases, the phonon-limited electron mobility μph increases to a maximum at tSi of ∼3 nm and decreases monotonically. The increase in mobility results from the increase of the fraction of electrons in the lowest energy subband that has a higher mobility than other subbands. The mobility decrease in the extremely thin tSi region is attributed to the enhancement of phonon scattering rates caused by a reduction of the spatial widths of the subbands.

The physical basis and the limitation for the universal mobility behavior of fully depleted silicon-on-insulator (SOI) metal–oxide–semiconductor Si inversion layers are shown by means of an analysis of the electronic states (potential profile, subband structure, and electron density distribution). As long as the top Si layer thickness is larger than the inversion layer thickness and the electron density is much higher than the impurity concentration in the inversion region, it is proved that the electronic states of an SOI Si inversion region are equivalent to those of a certain bulk Si inversion region. In this context, the definition of the effective vertical electric field Eeff for SOI inversion layers is derived and it ensures the identical mobility dependence on Eeff for SOI and bulk Si inversion layers. The effective carrier mobility μeff behavior in SOI Si inversion layers is universal, irrespective of structural parameters or back gate voltages, over the Eeff range where the mobility is essentially limited by phonon scattering and/or surface roughness scattering at the upper interface. On the other hand, when the electron density distribution of the inversion region reaches the lower surface of the top Si layer sufficiently, it is predicted that the universal mobility behavior is not maintained, but there exists another kind of mobility behavior which is dependent on the top Si layer thickness. Moreover, self-consistent calculations for the electronic states clarify the range where the equivalence of the electronic states for SOI and bulk Si inversion regions holds as function of the effective field Eeff, the top Si layer thickness, and the top Si layer impurity concentration. The phonon-limited mobility is also evaluated to confirm the equality of the mobility for SOI and bulk Si inversion regions.

The physical origin of gate capacitance in both bulk and silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is studied. The gate capacitance is theoretically derived as the series capacitance comprising the oxide capacitance, number capacitance (CN), level capacitance (Clevel), and field capacitance (Cfield). CN is in proportion to the thermodynamic density of states under the hypothetical condition that the subband energy levels remain constant when the total electron density is differentiated by the Fermi level. Clevel is inversely proportional to the result of differentiating the subband energy level by the total electron density. In the case of bulk MOSFETs or SOI MOSFETs with thick buried oxide, Cfield, which originates from the electric field at the edge of the depletion layer, is negligible. In addition to the fact that our new theoretical model corresponds to the intuitive conventional model expressed in terms of the effective thickness of the inversion layer in bulk MOSFETs, it is demonstrated that the conventional capacitance model is also applicable to SOI MOSFETs at 300 K. We have calculated self-consistently the capacitance of a bulk MOSFET and of SOI MOSFETs with various top-silicon layer thicknesses at 300 K. At the fixed total electron density near 1012 cm−2, the gate capacitance becomes large with decreasing top-silicon layer thickness. This difference in the gate capacitance mainly comes from Clevel, which means that in the case of SOI MOSFETs with a thin top-silicon layer, a small increase in the subband energy level with increasing electron density results in large gate capacitance and high performance of the SOI MOSFETs at 300 K.

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