Optimization of saddle junctionless FETs for extreme high integration

Jin, Xiaoshi; Wu, Meile; Liu, Xi; Lee, Jung‐Hee; Lee, Jong‐Ho

doi:10.1007/s10825-016-0830-5

Cited by 5 publications

(2 citation statements)

References 18 publications

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“…The shorter channel is less immune to the SCEs, and the distance between gate and source/drain contact is decreased, which triggers the prominent leakage current. In our previous work, we proposed novel saddle JL FETs which need no additional chip area to be occupied (or in other words, the integration can be maintained with the same level as double‐gate or triple‐gate JL FETs) but realize more excellent performance comparing with conventional double‐gate or triple‐gate JL FETs . The novel structure has another 2 vertical channels which increase the effective channel length without occupying additional chip area, so the distance between the source and drain electrode is lengthened, which weakens the effects mentioned above.…”

Section: Introductionmentioning

confidence: 99%

A novel low leakage saddle junctionless FET with assistant gate

Jin

Gao

Yang

et al. 2018

Int J Numerical Modelling

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In this paper, a novel low leakage saddle junctionless field effect transistor with assistant gate is proposed. Its electrical properties have been extensively investigated by studying the influence resulting from variation of design parameters, such as the thickness of assistant gate, oxide layer thickness between the main and assistant gate, extension height of S/D contact, and the voltage of assistant gate. Compared with conventional structure, the proposed saddle junctionless field effect transistor with assistant gate shows much better performance at off state. The leakage current is effectively restrained, and the I on -I off ratio is largely improved. Design parameter optimization has also been performed.

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Section: Introductionmentioning

confidence: 99%

A novel low leakage saddle junctionless FET with assistant gate

Jin

Gao

Yang

et al. 2018

Int J Numerical Modelling

Self Cite

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“…Mohammad Bavir et al studied the performance of a JLDG (Double gate) MOSFET with and without symmetrical side gates. 39 The schematic structure is being represented in Fig. 3.…”

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confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

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Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

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