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Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

This article proposes an analytical charge-based model that incorporates interface trapping. The model's applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with TCAD device simulation results and available experimental data from the literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction-Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device's characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

A novel Gate All Around Negative Capacitance Junction less FET (GAA-NC-JLFET) is proposed in this work, where different RF/Analog, Linear, and Non-linear parameters were investigated for different ferroelectric thickness in depth. The simulation result is calibrated with the available experimental data from literature. Adding a layer of ferroelectric material to a JLFET is a good means of decreasing short channel effects when compared to typical GAA JLFETs. The effect of ferroelectric layer thickness on DC parameters such as drain current (IDS), subthreshold swing (SS), threshold voltage (Vth), and Ion/Ioff as well as linear parameters such as transconductance coefficients (gm2 and gm3), voltage intercept points (VIP2 and VIP3), and input intercept point (IIP3) have been studied. Furthermore, this paper investigates non-linearity parameters such as harmonic distortion and intermodulation distortion in relation to various ferroelectric thicknesses. The TCAD device simulator was extensively used to conduct this analysis, and the results revealed that increasing the ferroelectric layer resulted in a significant improvement in the values of RF and linear parameters, as well as a decrease in the values of non-linearity parameter values, resulting in an increase in the device's linearity, which can be used in wide range of RFIC applications.

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