A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

Abstract

This article proposes an analytical charge-based model that incorporates interface trapping. The model's applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with TCAD device simulation results and available experimental data from the literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction-Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device's characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

Performance analysis of GaN‐FINFET for RFIC application with respect to different FinWidth's

“…The impact of various fin width's on drain to source current is shown in linear scales in Figure 7. It is seen that, owing increase in the total gate width, higher fin width implies an increase in the drain current 16 . The plot clearly shows that as the Fin width decreases the threshold voltage starts increasing, in other way increase in the Fin width leads to the reduction in the threshold voltage, as the threshold voltage of the device gradually increases whereas it decreases the device ON‐current I on .…”

“…It is seen that, owing increase in the total gate width, higher fin width implies an increase in the drain current. 16 The plot clearly shows that as the Fin width decreases the threshold voltage starts increasing, in other way increase in the Fin width leads to the reduction in the threshold voltage, as the threshold voltage of the device gradually increases whereas it decreases the device ON-current I on . Whereas the OFF-current (leakage current) I OFF of the device also starts increasing as the Fin Width starts increasing as shown in the log scale of Ids-Vds characteristics in Figure 8.…”

RF and Linearity Analysis of Heterojunction-free Ga2O3 FINFET with Respect to Different Fin Widths and Temperatures

“…15 and 16 it is neat that g m2 and g m3 start to increase with the increase in the width of the fin, the crucial reason for this can be said as the rise in the leakage current/OFFcurrent value along with the increase in the width of the fin. 24 The increase in the temperature makes both the values of g m2 and g m3 fall gradually, as the I on current is low at the high temperature. Hence highest g m2 and g m3 could be obtained at low temperature.…”

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

“…GAA effectively control shortchannel effects. 15 Due to its exceptional electrical characteristics, such as their superior short-channel gate control even if current transport is constrained by the size of the nanowires, GAA silicon Junctionless FETs 16 are a formidable challenge for nanosheet devices. When the device is scaled down, this improves gate controllability in comparison to traditional devices, reduces power dissipation, and also makes it possible to incorporate nanowires more easily in greater density arrays.…”