Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Abstract

Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

Composition-Dependent Phonon and Thermodynamic Characteristics of C-Based XxY1−xC (X, Y ≡ Si, Ge, Sn) Alloys

“…Since the invention of Si-based transistors [1], the evolution to include them in radio frequency (RF) devices for microelectronics has been remarkable [2][3][4][5][6][7][8][9][10][11]. With the low processing costs, Si-technology has led to many achievements by incorporating electrodes, dielectrics, and other elements in different integrated circuits (ICs).…”

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

“…However, major challenges have to be overcome to establish the feasible implementation of JL transistors in low-power switching applications [ 5 , 7 ]. Typically, the ON-current of ∼10 −3 A/μm and the OFF-current of ∼10 10 A/μm are the design targets for low-power switching devices.…”

“…Typically, the ON-current of ∼10 −3 A/μm and the OFF-current of ∼10 10 A/μm are the design targets for low-power switching devices. At present, one of the major challenges for JLFET structures in low-power and ultra-low-power switching applications is random dopant fluctuation (RDF) [ 7 ]. Ion implantation causes discrete and random dopant insertion in the silicon layer during the doping process, leading to an implausible uniform doping, more potential shift, and less mobility [ 7 ].…”

2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue

“…One major well-known and thoroughly investigated drawback of FET devices is short-channel effect [26][27][28] which leads to invention of several new architectures [29][30][31][32][33][34][35] including junctionless devices [36,37]. A perfect blend of junctionless device with dual material double gate (DMDG) architecture leads to lowering of subthreshold swing, optimizing DIBL, roll off of threshold as well improvement of ON-to-OFF current ratio [38].…”