A novel low leakage saddle junctionless FET with assistant gate

Abstract

In this paper, a novel low leakage saddle junctionless field effect transistor with assistant gate is proposed. Its electrical properties have been extensively investigated by studying the influence resulting from variation of design parameters, such as the thickness of assistant gate, oxide layer thickness between the main and assistant gate, extension height of S/D contact, and the voltage of assistant gate. Compared with conventional structure, the proposed saddle junctionless field effect transistor with assistant gate shows much better performance at off state. The leakage current is effectively restrained, and the I on -I off ratio is largely improved. Design parameter optimization has also been performed.

Performance analysis of short channel effects immune JLFET with enhanced drive current

“…The A V can be used to get the maximum possible voltage gain of any transistor regardless of the biasing. The highest value of A V was found to be 16.47 dB at for and , which is comparatively better than the experimental result of FinFETs (~15 dB) 24 . The early voltage obtained in the accumulation region for the SGO HB JLFET is very high ~44.33 V at for and and ~9.89 V at for and .…”

“…The highest value of A V was found to be 16.47 dB at V DS ¼ 1 V for T SGO ¼ 5 nm and L SGO ¼ 10 nm, which is comparatively better than the experimental result of FinFETs ($15 dB). 24 The early voltage obtained in the F I G U R E 7 Variation of I ON /I OFF current ratio, subthreshold swing and DIBL for different channel lengths F I G U R E 8 Transfer characteristics of SGO HB JLFET with variation in the length (L SGO ) and thickness (T SGO ) of step-gate-oxide accumulation region for the SGO HB JLFET is very high $44.33 V at V GS ¼ 2 V for T SGO ¼ 6 nm and L SGO ¼ 12 nm and $9.89 V at V GS ¼ 2 V for T SGO ¼ 2 nm and L SGO ¼ 4 nm. This higher value of early voltage is due to the smaller value of g d , which shows that SGO HB JLFET has better control on the channel length modulation.…”

“…Since the channel carrier concentration is controlled by gate, the valence band and the conduction band are overlapped at the channel/drain interface and a lateral band‐to‐band tunneling (BTBT) of electrons occurs 18 that leads to gate induced drain leakage (GIDL) 20 and hence OFF‐state current increases. To decrease the OFF‐state leakage current caused by GIDL effect, many structures have been proposed such as a saddle JLFET with assisted gate, 24 dual‐material dual gate JL MOSFET embedded with low doped buried layer, 25 charge plasma JLFET with contact engineering, 26 JLFET with hybrid channel, 27 JLFET with high‐k BOX, 28 JLFET with dual material gate, 29 JLFET with core‐shell architecture 30 and so on.…”

A High-Performance Rectangular Gate U Channel FETs with Only 2-nm Distance between Source and Drain Contacts

“…The distance between source and drain contacts is more realistic and effective because the final goal of the design of the nano-scale device is the realization of the best performance in a limited given chip area, and the actual device size is related to the channel width and the distance between source and drain contacts. In order to combine the advantages of both the MG FETs and recessed channel MOSFETs, in our previous work, we proposed saddle-shaped gate FETs with a U-shaped channel [21–23], which promotes the gate controllability to the horizontal channel part of the recessed channel from a planar single-gate type to a 3-D triple-gate type. After that, we upgrade this 3-D triple-gate feature formed not only in the horizontal channel part but also in both vertical channel parts.…”