Electromigration Cu mass flow in Cu interconnections

Hu, C.‐K.; Canaperi, D.; Chen, S.T.; Gignac, L.; Kaldor, S.; Krishnan, M.; Malhotra, S. G.; Liniger, E.; Lloyd, J. R.; Rath, D.L.; Restaino, D.; Rosenberg, R.; Rubino, J. Germán; Seo, Soon‐Cheon; Simon, A.; Smith, Sharon L.; Tseng, Wei–Tsu

doi:10.1016/j.tsf.2005.09.161

Cited by 32 publications

(14 citation statements)

References 13 publications

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“…Two methods, namely, the alloying of Cu interconnects [10] and the replacing of the dielectric cap on the Cu top surface with a metal cap [11], were widely investigated to increase the diffusion activation energy of Cu interconnects. A lot of work has been carried out to research the new EM-resistant alloys; alloying element such as Al [12], Cr [13], Pd [14], Zr [15], and Ag [16] have been added into Cu to improve the properties of the thin-film Cu.…”

Section: Introductionmentioning

confidence: 99%

Study of the effects of an adatom Sn on the Cu surface electromigration using a first principles method

Liu

Lü

et al. 2007

Applied Surface Science

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Section: Introductionmentioning

confidence: 99%

Study of the effects of an adatom Sn on the Cu surface electromigration using a first principles method

Liu

Lü

et al. 2007

Applied Surface Science

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“…The papers [5]- [7] describe the basic physical failure mechanism of EM, and works [8]- [11] report tools for EM analysis and detection. However, there are only a few studies of the circuit configurations and interconnect structures sensitive to EM effect [25].…”

Section: Introductionmentioning

confidence: 99%

On-chip em-sensitive interconnect structures

Marek-Sadowska

Lee

2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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Due to ever greater current densities in modern IC designs, electromigration (EM) in copper interconnects has become an important reliability factor. In this paper, we analyze current densities on bus and clock networks. We observe that under certain conditions, these networks may become sensitive to EM effects and prone to failure. We perform SPICE simulations on open source Wishbone bus and non-tree clocks for IBM and ISCAS89 benchmarks. Experiments on these networks show that on some wire segments current may flow predominantly in one direction and its density may exceed the maximum allowed values suggested by the International Technology Roadmap for Semiconductors (ITRS). When power network experiences noise, the links of a non-tree clock may carry currents whose densities could be 100 times greater than those of the tree branches. In our study, we compare various methods of reducing the EM effect on interconnects. We demonstrate that in comparison to such design methods as increasing wire widths, reducing circuit frequency or decreasing driver sizes, the technology-based solution of capping copper (Cu) wires with cobalt tungsten phosphide (CoWP) coating works best and eliminates EM violations without area overhead, performance loss or additional design effort.

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“…There is much research interest in the fabrication of CoWP film for its use as a barrier/capping layer of copper interconnection in microelectronic devices [1][2][3][4][5][6][7][8][9]. Copper is a better candidate for metallization in ultra-large scale integration (ULSI) than aluminium because of its higher allowed current density, good reliability and higher electromigration resistance [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…There are some reports in the literature on the fabrication of CoWP film on a copper substrate by an electroless deposition method from aqueous solution [1][2][3][4][5][6][7][8][9]. However, the electroless deposition is very much selective and requires higher processing temperature.…”

Section: Introductionmentioning

confidence: 99%