▪ Abstract  The increasingly rapid transition of the electronics industry to high-density, high-performance multifunctional microprocessor Si technology has precipitated migration to new materials alternatives that can satisfy stringent requirements. One of the recent innovations has been the substitution of copper for the standard aluminum-copper metal wiring in order to decrease resistance and tailor RC delay losses in the various hierarchies of the wiring network. This has been accomplished and the product shipped only since the fall of 1998, after more than a decade of intensive development. Critical fabrication innovations include the development of an electroplating process for the copper network, dual-damascence chem-mech polishing (CMP), and effective liner material for copper diffusion barrier and adhesion promotion. The present copper technology provides improved current-carrying capability by higher resistance to electromigration, no device contamination by copper migration, and the performance enhancement analytically predicted. This success of the shift to copper will accelerate the industry movement to finer features and more complex interconnect structures with sufficient device density and connectivity to integrate full systems on chips. The next innovation will be the introduction of low-dielectric constant material that, in combination with copper, will create added excitement as the industry learns how to utilize this new capability.

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small as-deposited grain size is shown to be consistent with grain boundary pinning by a fine dispersion of particles or other pinning sites. In addition, room temperature diffusion of the pinning species along copper grain boundaries is shown to be adequate to allow the onset of abnormal grain growth after an initial incubation time, with a transient time inversely proportional to film thickness.

Electromigration in 0.15–10 μm wide and 0.3 μm thick Cu lines deposited by physical vapor deposition has been investigated using both resistance and edge displacement techniques in the sample temperature range 255–405 °C. For wide polycrystalline lines (>1 μm), the dominant diffusion mechanism is a mixture of grain boundary and surface diffusion, while in narrow lines (<1 μm) the dominant mechanism is surface transport. The activation energy for grain-boundary transport is approximately 0.2 eV higher than that of surface transport.

Texture analysis of damascene-fabricated Cu lines by x-ray diffraction and electron backscatter diffraction and its impact on electromigration performance Electromigration in on-chip Cu interconnections with a selective electroless metal coating, CoWP, CoSnP, or Pd, on the top surface of Cu damascene lines has been investigated. The 10-20 nm thick metal cap significantly improves electromigration lifetime by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure by electromigration.

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Electromigration in Cu Damascene lines with bamboo-like grain structures, either capped with Ta/TaN, SiNx, SiCxNyHz layers, or without any cap, was investigated. A thin Ta/TaN cap on top of the Cu line surface significantly improves electromigration lifetime when compared with lines without a cap and with lines capped with SiNx or SiCxNyHz. The activation energy for electromigration increased from 0.87 eV for lines without a cap to 1.0–1.1 eV for samples with SiNx or SiCxNyHz caps and to 1.4 eV for Ta/TaN capped samples.

Electromigration-induced stress distributions in 200 μm long, 10 μm wide aluminum conductor lines in 1.5 μm SiO2 passivation layers have been investigated in real time using synchrotron-based white-beam x-ray microdiffraction. The results show that a steady-state linear stress gradient along the length of the line developed within the first few hours of electromigration and that the stress gradient could be manipulated by controlling the magnitude and the direction of the current flow. From the current density dependence of the steady-state stress gradient, the effective valence Z* was determined to be 1.6 at 260 °C. From the time dependence of the transient-state stress gradient, the effective grain boundary diffusion coefficient Deff was estimated to be 8.2×10−11 cm2/s at 260 °C using Korhonen’s stress evolution model [M. A. Korhonen, P. Bo/rgesen, K. N. Tu, and C.-Y. Li, J. Appl. Phys. 73, 3790 (1993)]. Both Z* and Deff values are in good agreement with the previously reported values.

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