Reduced electromigration of Cu wires by surface coating

Hu, C.‐K.; Gignac, Lynne; Rosenberg, R.; Liniger, E.; Rubino, J. Germán; Sambucetti, C.J.; Domenicucci, A.; Chen, X.; Stamper, A. K.

doi:10.1063/1.1504491

Cited by 220 publications

(128 citation statements)

References 5 publications

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“…392,393 CoWP and CoSnP are two passivating metals that have been commonly reported in the literature that can be electrolessly plated on Cu and that have been utilized to increase the electromigration resistance of DB/Cu interfaces by >100X. The primary drawbacks to this approach are the difficulty of achieving perfect selectivity in the presence of inevitable surface defects, compatibility of the selective metal caps with next metal layer patterning and cleaning steps, and the added cost associated with the additional processing step.…”

Section: Current Status Of Low-k Db/ccl/es Materials and R And Dmentioning

confidence: 99%

“…Many of the reported methods involve either doping the Cu lines with a few percent of select alloying elements, [376][377][378][379][380][381][382] or selectively forming an additional surface passivation layer material between the DB and Cu. [383][384][385][386][387][388][389][390][391][392][393] In most cases, these methods involve additional processing steps separate from the DB deposition process. However, one method that has been integrated with the DB deposition involves selectively forming a CuSiN interfacial layer between the DB and Cu.…”

Section: Current Status Of Low-k Db/ccl/es Materials and R And Dmentioning

confidence: 99%

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Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

124

111

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: Current Status Of Low-k Db/ccl/es Materials and R And Dmentioning

confidence: 99%

Section: Current Status Of Low-k Db/ccl/es Materials and R And Dmentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

124

111

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“…23 With a suitable choice of metallic layer, the adhesive energy at the interface can be significantly increased and this has been suggested to slow the rate of interfacial electromigration of Cu. The most commonly used metal cap layers are either an electro-deposited CoWP alloy, 24,25 or Cu silicide.…”

Section: Improvement Strategies For the Drift Velocitymentioning

confidence: 99%

Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

Oates

2014

ECS J. Solid State Sci. Technol.

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A key element for future silicon IC technology development is the containment of electromigration -induced failure of Cu / low-k interconnects. Continued progress in meeting electromigration reliability requirements for future technology nodes will require a multi-faceted approach to the problem: first the development of effective process solutions to limit the impact of technology scaling on electromigration life-time reduction; and second, the provision of models of failure that are representative of circuit operation to determine realistic current-limiting design rules. We will show that process solutions involve limiting the rate of transport along interfaces and grain boundaries in the damascene trench architecture using metal capping layers and Cu alloys. Most models of electromigration failure have been developed using DC stress conditions, while circuits predominantly operate with non-DC (pulsed DC or AC) signals. Understanding the relationship between failure under DC and non-DC conditions is a necessary aspect of realistic reliability characterization. In this paper we review: our recent studies that establish the relationship between Cu microstructure, metallic capping and dilute Cu alloy additions and thereby identify effective scenarios for mitigation with technology scaling; and experimental studies of electromigration failure under non-DC stress that explore the physical mechanisms involved. Electromigration failure of interconnects has been a long-standing concern for the development of highly reliable integrated circuits (IC). Despite intense efforts following the first observation of electromigration -related failure of Al circuit interconnects in 1966, 1 it has proven impossible to find a robust process solution by material modification for either Al or the more recently introduced Cu metal system. It remains an issue that can only be partially mitigated with process solutions, and ultimately it is controlled at the circuit level by the use of current limiting design rules. There is a prevalent concern that this method of control of the rate of electromigration failure will be detrimental to circuit performance. Therefore, during technology development, a balance must be found to ensure circuit performance is maintained without seriously impairing electromigration reliability. Achieving this balance requires a thorough fundamental understanding of the factors that determine the efficacy of process mitigation techniques. Moreover, current limiting design rules are extrapolated from accelerated test data using models of the failure mechanism, and the models must accurately reflect the physical mechanisms of failure.For the most advanced Si process technologies currently being manufactured with Cu and low-k dielectrics, electromigration failure times have decreased rapidly with technology progression, adding urgency to the problem of assuring electromigration reliability. Fig. 1 shows the reduction in failure time for both long conductor lengths and for shorter lengths; 2,3 for the latter, the Bl...

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“…2c. Note that neither the substrate nor the dielectric encapsulation layer is used for the measurement, which enhances heat dissipation and suppresses interfacial diffusion 18,19 . The J max value of MF1 is similar to that of the pristine CNT fiber even though decoration by Cu particles is expected to reduce the contact resistance between CNTs and enhance the efficiency of heat dissipation at the contacts.…”

Section: Ampacity Measurementsmentioning

confidence: 99%

Metal nanofibrils embedded in long free-standing carbon nanotube fibers with a high critical current density

Rho

Park

et al. 2018

NPG Asia Mater

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With the growth of nanoelectronics, the importance of thermal management in device packaging and the improvement of high-current-carrying interconnects/wires for avoiding the premature failure of devices have been emphasized. The heat and electrical transport properties of the bulk may not be valid in the characterization of a material at the nanometer level, because the phenomena that occur at the interfaces and grain boundaries become dominant. The failure mechanism of bulk metal interconnects has been understood in the context of electromigration; however, in nanoscale materials, the effect of the heat dissipation that occurs at the nanointerfaces may play an important role. Here, we report the preparation of continuous carbon nanotube (CNT)-Cu composite fibers that possess Cu nanofibrillar structures with a high current-carrying capacity. Various-shaped CNT-Cu microfibers with different Cu grain morphologies were produced via Cu electroplating on continuous CNT fibers. Cu fibril structures were embedded in the voids inside the CNT fiber during the early stage of electrodeposition. The temperaturedependent and magnetic field-dependent electrical properties and the ampacity of the produced CNT-Cu microfibers were measured, and the failure mechanism of the fiber was discussed. The interconnection of Cu nanograins on the surface of the individual CNTs contributed to the enhancement in the charge-carrying ability of the fiber. The effective ampacity of the Cu nanofibrils was estimated to be~1 × 10 7 A/cm 2 , which is approximately 50 times larger than the ampacity measured for a bulk Cu microwire.

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Reduced electromigration of Cu wires by surface coating

Cited by 220 publications

References 5 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

Metal nanofibrils embedded in long free-standing carbon nanotube fibers with a high critical current density

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