Copper plating baths used for forming integrated circuit interconnects typically contain three or four component additive mixtures which facilitate the superfilling of via holes and trench lines during damascene plating. Extensive study over the last two decades has provided researchers with an understanding of the underlying mechanisms. The role of cuprous intermediates in the copper deposition reaction has long been acknowledged, but it is not yet fully understood. In this paper we describe the results of an electrochemical study of the interaction of the organic additives used with copper and copper ions in solution. It is shown that cuprous intermediates near the copper surface affect the overpotential and the kinetics of plating. The additives regulate the presence of cuprous species on the surface; levelers and suppressors inhibit Cu þ formation, whereas accelerating additives enhance Cu þ formation. Acceleration by the bis(sodiumsulfopropyl) disulfide (SPS) additive results from accumulation of cuprous complexes near the surface. Adsorbed cuprous thiolate [Cu(I)(S(CH 2) 3 SO 3 H) ad ] is formed through interaction of Cu þ ions and SPS rather than Cu 2þ and mercaptopropane sulfonic acid (MPS).
We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small as-deposited grain size is shown to be consistent with grain boundary pinning by a fine dispersion of particles or other pinning sites. In addition, room temperature diffusion of the pinning species along copper grain boundaries is shown to be adequate to allow the onset of abnormal grain growth after an initial incubation time, with a transient time inversely proportional to film thickness.
On-chip interconnections comprise a multilevel structure of fine wiring located on the top of the transistor circuitry of logic or memory chips, whose role is to connect circuits together as shown in Fig. 1. To avoid significant degradation of circuit speed, on-chip interconnections should permit rapid signal transmission among the various parts of the circuitry. Ever since the development of the integrated circuit about 40 years ago, the most pervasively used materials for the fabrication of the wiring structure have been aluminum as the conductor (or more recently an aluminum-copper alloy for better reliability) and silicon dioxide as the insulator. The transition to copper as the conductor and to a better insulator began with IBM’s announcement in September 1997 and product shipment since June 1998. This signals one of the most important changes in materials that the semiconductor industry has experienced since its creation. Copper metallization was implemented first since significant gains can be obtained by copper alone.
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