Conductance slope and curvature coefficient of InGaAs/GaAsSb heterojunctions at varying band alignments and its implication on digital and analog applications

Abstract

We assess InGaAs/GaAsSb heterojunctions at varying band alignments for applications in both tunnel field effect transistors (TFETs) as well as for nonlinear analog components such as millimeter wave detectors. We use conductance slope measurements as a fundamental figure of merit, as it is not affected by the three-terminal parasitics of subthreshold-slope in a TFET and represents the ideal subthreshold slope intrinsic to the junction in the absence of three-terminal parasitics. We prove that conductance slope/subthreshold slope is not equivalent to curvature coefficient, indicating that it is actually easier to exceed the thermal limit of curvature for analog applications than it is to exceed the subthreshold slope limit for digital applications. In addition, we show that no published heterojunction that exceeds the curvature limit would be capable of exceeding the subthreshold slope limit. We experimentally demonstrate the formation of epitaxial InGaAs/GaAsSb heterojunctions at varying band alignments accomplished using lattice-mismatched epitaxy with graded buffers. We show a dependence of conductance slope on material quality, adding further proof that "steepness" is limited by materials defects and inhomogeneity. We demonstrate that the conductance slope does not depend on temperature for type-II band alignment, adding further proof that TFETs, which show strong temperature dependencies, are dominated by thermal parasitics. Finally, we develop and demonstrate an InGaAs/GaAsSb heterojunction system integrated on an InP platform with a record 76 mV/decade conductance slope and 43 V À1 curvature coefficient near zero-bias, with the capability of up to 60 V À1 curvature coefficient. V

Influence of Doping and Tunneling Interface Stoichiometry on n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki Diode Behavior

“…Both simulations and experimental studies are ongoing to answer this question and thus find the suitable doping for an ideal TFET operation. Also, the conductance curves (J/V vs V) for these 3 diodes at RT and 230K (figure 3b) show that the conductance slope is independent of the T which is in agreement with previous reports [12]. The conductance slope in ED3 is higher due to the higher degeneracy of the hole quasi Fermi level.…”

Investigation of Localized States in GaAsSb Epilayers Grown by Molecular Beam Epitaxy

“…To be specific, GaAsSb alloy can be applied in data-communication lasers in the range of 1.3–1.5 μm 12 13 14 15 16 17 and GaInAs/GaAsSb multi-quantum well (MQWs) have been used as the gain medium for 2–3 μm type-ІІ MQWs laser 18 . On the other hand, GaAsSb materials can be used for solar cell because their wide light absorption across the wavelength of solar radiation 19 20 21 , and infrared photodetectors applications 22 23 24 . Furthermore, the bandgaps can be achieved by varying Sb alloy composition in GaAsSb, which is internally lattice matched with InP-based devices 25 .…”

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

“…Output characteristics of both devices are shown in Figures 3(a) The drain conductance slope plot for the EOT ¼ 0.8 nm device. Such characteristics are reported 16,17 to be a measure of how steep the TFET may achieve. In strong on-state, the TFET operates as an Esaki diode.…”

“…terms of the on-state performance. The conductance slope 16,17 plot where the I d /V d is plotted against V d for various V g values is shown in Figure 3(d). In strong on-state (large V g bias) the TFET operates as an Esaki-diode and the conductance slope method should therefore be applicable.…”