Cache memory organization to enhance the yield of high performance VLSI processors

Abstract

Abstract-High-performance VLSI processors make extensive use of on-chip cache memories to sustain the memory bandwidth demands of the CPU. As the amount of chip area devoted to onchip caches increases, we can expect a substantial portion of the defects/faults to occur in the cache portion of a VLSI processor chip. considerably.This paper studies the tolerance of defects/faults in cache memories. We argue that, even though the major components of a cache are linear RAM's, traditional techniques used for fault/ defect tolerance in RAM's may neither be appropriate nor necessary for cache memories. We suggest a scheme that allows a cache to continue operation in the presence of defective/faulty blocks. We then present the results of an extensive trace-driven simulation analysis that evaluates the performance degradation of a cache due to defective blocks. From the results we see that the on-chip caches of VLSI processors can be organized such that the performance degradation due to a few defective blocks is negligible. We conclude that by tolerating such defects without a noticeable performance degradation, the yield of VLSI processors can be enhanced considerably.

Performance-effective operation below Vcc-min

“…A simple method is proposed that disables faulty cache blocks [19] at low voltage. The rationale for such method is based on observations regarding the distributions of faults in an array according to probability theory.…”

“…Block-disabling has been proposed by [15], [19] to increase processor yield and is used by modern processors [13] to continue operation in the presence of permanent-errors. In this work we consider it for lowvoltage operation.…”

“…Sohi [19] studied the performance impact of cache organization with disabled portions, such as ways and sets. The goal of that work was to improve yield without noticeable performance degradation.…”

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling

“…Another commonly used technique is Error Correcting Codes (ECC) [10][11] to deal with transient defects. ECC guarded memories can handle dynamic faults albeit at a heavy cost in power consumption, area and complexity [17]. Statistical sizing and optimization of the SRAM cell for yield enhancement is suggested in [12].…”

Selective wordline voltage boosting for caches to manage yield under process variations

“…In case of higher level caches (level 2 and 3), NUCA cache architecture [13] can be adopted to endure different cache access times due to process variations and hence eliminate the effect of increased access times on yields. Another conventional way to mitigate process variations in caches is to employ redundancy schemes [5][8] [11][19] [25][29] [32]. However, such schemes have considerable overhead.…”