Performance-effective operation below Vcc-min

Ladas, Nikolas; Sazeides, Yiannakis; Desmet, Veerle

doi:10.1109/ispass.2010.5452017

Cited by 16 publications

(20 citation statements)

References 23 publications

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“…Block disabling is implemented in modern processors operating at nominal voltages, and some authors advocate its use at lower voltages [26]; word disabling is similar to ours in complexity. Figure 8 shows the increase in MPKI for these techniques with respect to the unrealistically robust cell.…”

Section: Comparison With Prior Workmentioning

confidence: 80%

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Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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Abstract-Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100% of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression-and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2%, even when using small SRAM cells, which implies over 90% of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

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Section: Comparison With Prior Workmentioning

confidence: 80%

“…Lee et al examine performance degradation by disabling cache lines, sets, ways, ports, or the complete cache in a single processor environment [27]. To compensate for the associative loss, Ladas et al propose the implementation of a victim cache in combination with block disabling [26].…”

Section: Related Workmentioning

confidence: 99%

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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“…Block disabling techniques have been studied for operation at lower voltages because of their easy implementation and low overhead [14]. From the implementation perspective, only one bit per entry suffices.…”

Section: Impact Of Variability On Large Caches At Ultra-low Voltmentioning

confidence: 99%

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Ferrerón

Gracia

Alastruey-Benedé

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the threshold region has the promise of great energy savings. However, the potential savings of voltage scaling are limited by the correct operation of SRAM cells, which is not guaranteed below Vdd min , the minimum voltage in which cache structures operate reliably.Understanding the effects of operating below Vdd min requires complex modeling, so we introduce an updated probability failure model of SRAM cells at 22nm and explore the reliability impact of lowering the chip voltage supply below Vdd min in sharedmemory coherent chip-multiprocessors (CMP) running a variety of parallel workloads. A microarchitectural technique to cope with cache reliability at ultra-low voltages is block disabling; however, in many cases, the savings in on-chip caches do not compensate for the consumption in the rest of the system, as the consumption increase of the off-chip memory may offset the on-chip gain.We make the case that existing coherence mechanisms can provide the substrate to improve energy savings with block disabling and propose two low-complexity techniques. Taking the best of both techniques we can scale voltage below Vdd min and reduce system energy up to 39%, and system energy-delay up to 10%. Besides, by lowering the CMP consumption in a powerconstrained scenario, we could activate offline cores, reaching a potential speedup between 3.7 and 4.4.

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“…However, the study still relies on the execution of random maps which are generated by means of Monte Carlo method. Finally, there are several other studies [1], [21], [20], [10], [11] looking into the impact of faults over caches using random maps.…”

Section: Related Workmentioning

confidence: 99%

“…Previous block disabling-based studies (such as [22], [19], [21], [13], [12], [10], [20], [11]) rely on the use of an arbitrary number (small or large) of random fault-maps. Each random fault-map indicates faulty cache cell locations and determines the disabled faulty cache blocks.…”

Section: Introductionmentioning

confidence: 99%

An analytical model for the calculation of the Expected Miss Ratio in faulty caches

Sánchez¹,

Sazeides

Aragón³

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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Abstract-Technology scaling improvement is affecting the reliability of ICs due to increases in static and dynamic variations as well as wear-out failures. This is particularly true for caches that dominate the area of modern processors and are built with minimum-sized, but prone to failure, SRAM cells.Our attempt to address this cache reliability challenge is an analytical model for determining the implications on cache missrate of block-disabling due to random cell failure. The proposed model is distinct from previous work in that is an exact model rather than an approximation and yet it is simpler than previous work. Its simplicity stems from the lack of fault-maps in the analysis. The model capabilities are illustrated through a study of cache miss-rate trends in future technology nodes. The model is also used to determine the accuracy of a random fault map methodology.The analysis reveals, for the assumptions, programs and cache configuration used in this study, a surprising result: a relative small number of random fault maps, 100-1000, is sufficient to obtain accurate mean and standard-deviation values for the missrate. Additional investigation revealed that the cause of this behavior is a high correlation between the number of accesses and access distribution between cache sets.

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Performance-effective operation below Vcc-min

Cited by 16 publications

References 23 publications

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

An analytical model for the calculation of the Expected Miss Ratio in faulty caches

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