An analytical model for the calculation of the Expected Miss Ratio in faulty caches

Sánchez, Daniel; Sazeides, Yiannakis; Aragón, Juan L.; Garcia, Jose M.

doi:10.1109/iolts.2011.5994538

Cited by 7 publications

(6 citation statements)

References 25 publications

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“…In this section, we present an analytical model that can determine the EMR, SD_MR, and an approximate probability distribution of miss ratios (PD_MR) for a given program address trace, cache configuration, and random probability of permanent cell failure ( p f ail ) [Sánchez et al 2011]. The EMR captures the average degradation due to random faulty cells.…”

Section: Analytical Model For Cache Miss Rate Behavior In the Presencmentioning

confidence: 99%

Modeling the impact of permanent faults in caches

Sánchez

Sazeides

Cebrian

et al. 2013

ACM Trans. Archit. Code Optim.

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The traditional performance cost benefits we have enjoyed for decades from technology scaling are challenged by several critical constraints including reliability. Increases in static and dynamic variations are leading to higher probability of parametric and wear-out failures and are elevating reliability into a prime design constraint. In particular, SRAM cells used to build caches that dominate the processor area are usually minimum sized and more prone to failure. It is therefore of paramount importance to develop effective methodologies that facilitate the exploration of reliability techniques for caches.To this end, we present an analytical model that can determine for a given cache configuration, address trace, and random probability of permanent cell failure the exact expected miss rate and its standard deviation when blocks with faulty bits are disabled. What distinguishes our model is that it is fully analytical, it avoids the use of fault maps, and yet, it is both exact and simpler than previous approaches. The analytical model is used to produce the miss-rate trends (expected miss-rate) for future technology nodes for both uncorrelated and clustered faults. Some of the key findings based on the proposed model are (i) block disabling has a negligible impact on the expected miss-rate unless probability of failure is equal or greater than 2.6e-4, (ii) the fault map methodology can accurately calculate the expected miss-rate as long as 1,000 to 10,000 fault maps are used, and (iii) the expected miss-rate for execution of parallel applications increases with the number of threads and is more pronounced for a given probability of failure as compared to sequential execution.

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Section: Analytical Model For Cache Miss Rate Behavior In the Presencmentioning

confidence: 99%

Modeling the impact of permanent faults in caches

Sánchez

Sazeides

Cebrian

et al. 2013

ACM Trans. Archit. Code Optim.

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“…The term M i represents the expected number of additional misses due to faulty blocks. M i can be obtained analytically for a given cell pfail without using faultmaps as proposed in [27] 3 . To determine M i , we first compute the probability of a cache block failure p b f with Eq.…”

Section: Expected Etv I and M I For A Given Cell Pfailmentioning

confidence: 99%

“…If more accuracy is needed, future work can consider the detail interaction between units [30,14]. 3 The model used in this section to estimate M i is from [27] and is presented here for completeness.…”

Section: Why Are Etv I S Additive?mentioning

confidence: 99%

“…They estimate the expected miss ratio for a fixed number of faults by generating all the possible distributions of these faults over the cache sets. In [27], a methodology is proposed to estimate the expected miss rate and its expected distribution by using pfail without the need to generate fault maps. Our work shares similarities to [27] but, as highlighted in the introduction, also some key differences.…”

Section: Related Workmentioning

confidence: 99%

“…A recent relevant study [27] proposes a method that given a cache, random probability of permanent cell failure, and an address trace, can calculate without any fault-maps the expected miss ratio when blocks with permanent faults are disabled. The model proposed in our paper, augments the method in [27], to predictors, can produce for caches and predictors the miss-rate and misprediction distribution bounds respectively, and provides the expected performance and performance distribution bounds for individual or combination of faulty arrays.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

Hardy

Sideris²,

Ladas³

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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This paper presents a first-order analytical model for determining the performance degradation caused by permanently faulty cells in architectural and non-architectural arrays. We refer to this degradation as the performance vulnerability factor (PVF).The study assumes a future where cache blocks with faulty cells are disabled resulting in less cache capacity and extra misses while faulty predictor cells are still used but cause additional mispredictions.For a given program run, random probability of permanent cell failure, and processor configuration, the model can rapidly provide the expected PVF as well as lower and upper PVF probability distribution bounds for an individual array or array combination.The model is used to predict the PVF for the three predictors and the last level cache, used in this study, for a wide range of cell failure rates. The analysis reveals that for cell failure rate of up to 1.5e-6 the expected PVF is very small. For higher failure rates the expected PVF grows noticeably mostly due to the extra misses in the last level cache. The expected PVF of the predictors remains small even at high failure rates but the PVF distribution reveals cases of significant performance degradation with a non-negligible probability.These results suggest that designers of future processors can leverage trade-offs between PVF and reliability to sustain area, performance and energy scaling. The paper demonstrates this approach by exploring the implications of different cell size on yield and PVF.

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