Modeling the impact of permanent faults in caches

Abstract

The traditional performance cost benefits we have enjoyed for decades from technology scaling are challenged by several critical constraints including reliability. Increases in static and dynamic variations are leading to higher probability of parametric and wear-out failures and are elevating reliability into a prime design constraint. In particular, SRAM cells used to build caches that dominate the processor area are usually minimum sized and more prone to failure. It is therefore of paramount importance to develop effective methodologies that facilitate the exploration of reliability techniques for caches.To this end, we present an analytical model that can determine for a given cache configuration, address trace, and random probability of permanent cell failure the exact expected miss rate and its standard deviation when blocks with faulty bits are disabled. What distinguishes our model is that it is fully analytical, it avoids the use of fault maps, and yet, it is both exact and simpler than previous approaches. The analytical model is used to produce the miss-rate trends (expected miss-rate) for future technology nodes for both uncorrelated and clustered faults. Some of the key findings based on the proposed model are (i) block disabling has a negligible impact on the expected miss-rate unless probability of failure is equal or greater than 2.6e-4, (ii) the fault map methodology can accurately calculate the expected miss-rate as long as 1,000 to 10,000 fault maps are used, and (iii) the expected miss-rate for execution of parallel applications increases with the number of threads and is more pronounced for a given probability of failure as compared to sequential execution.

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

“…The first approach consists of using low-level fault models and applying them directly to the possible injection targets. Typical TSIM injection targets are the different memory structures like, RAM and caches [24], and the architectural registers [13], [25]. The second approach consists on defining specific microarchitectural level fault models affecting specific microcontroller modules.…”

A fault-tolerant last level cache for CMPs operating at ultra-low voltage

“…One challenge for analyzing fault mitigation techniques is the large set of required simulations. Running all workloads and simulated models combinations for a single fault map can lead to wrong results, as other authors have described [32,33]. For example, if all the faults affect to the most/least frequently accessed cache sets, the observed speed-up would be much lower/higher than in reality.…”

Characterizing fault propagation in safety-critical processor designs

“…In fact, the majority of the potential injection nodes that are present at more detailed abstraction levels like RTL or gatelevel are missing. Typically, fault injection experiments using microarchitectural simulators focus on the register file [8] [19] and on the different memory structures [18] [1]. However, these fault injection experiments, while useful to test the effectiveness of fault-tolerant capabilities and the like, are not suitable to estimate failure rate metrics as required by certification standards.…”