Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling

Sasan,; Homayoun,; Eltawil, Ahmed M.; Kurdahi, Fadi

doi:10.1109/date.2009.5090795

Cited by 19 publications

(12 citation statements)

References 13 publications

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“…There have been several efforts at the device level to investigate custom SRAM architectures to improve the reliability of embedded memories, from re-arrangement of the physical-addresses [76], the introduction of customized logic [84], and different cell sizes [17], [53], [72] at the cost of increases in area.…”

Section: B Reliable Memory Subsystemsmentioning

confidence: 99%

Software Controlled Memories for Scalable Many-Core Architectures

Bathen

Dutt

2012

2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

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Technology scaling along with the ever evolving demand for media-rich software stacks have motivated the need for many-core platforms. With the increase in compute power and its inherent demand for high memory bandwidth comes the need for vast amounts of on-chip memory space. Thus, designers must carefully provision the memory real-estate to meet their application's needs. It has been shown in the embedded systems domain that both software controlled memories (e.g., scratchpad memories) and hardware-controlled memories (e.g., caches) have their pros and cons, some application domains such as multimedia fit very well in the software-controlled memory model, while other domains such as databases work well with caches. As a result, efficient memory management is extremely critical as it has a great impact on the system's power consumption and throughput. Traditional memory hierarchies primarily consist of SRAM-based onchip caches, however, with the emergence of non-volatile memories (NVMs) and mixed-criticality systems, on-chip memories will be heterogeneous, not only in type (cache vs. scratchpad) but also in technology (e.g., SRAM vs. NVM). This paper surveys the state of the art in memory subsystems for many-core platforms, and presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the various challenges designers face in deploying such memory subsystems (e.g., sharing the memory resources, accounting for variations in the subsystem, etc.).

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Section: B Reliable Memory Subsystemsmentioning

confidence: 99%

Software Controlled Memories for Scalable Many-Core Architectures

Bathen

Dutt

2012

2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

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“…Though many techniques have been proposed for leakage reduction of the cache memories [4][5] [6] [7][8] [9] [10], the main contribution of our technique is addressing both SRAM failure-and leakage-induced yield losses under process variation in 3D microprocessors. To the best of our knowledge, this is the first work which considers both SRAM failures and leakage-induced yield losses in 3D microprocessors.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Kong

Koushanfar

Chung

2015

IEEE Trans. Comput.

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As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., diestacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrowwidth values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

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“…The hard errors can appear due to process variation, aging, and others [4] [5] [6]. As described in [1] an effective graceful degradation method for set associative cache memories called SAM (Self Adaptive cache Memories) was proposed.…”

Section: Introductionmentioning

confidence: 99%

Improving performance and area overhead by reducing the switching table for Self Adaptive cache Memories

Agnola

Vlăduţiu

Udrescu

et al. 2011

2011 IEEE 17th International Symposium for Design and Technology in Electronic Packaging (SIITME)

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This paper proposes a number of improvements for the switching table used by the Self Adaptive cache Memories (SAM) method, as described in [1]. The Switching Table is used for maintaining performance in a continuously degrading memory. The proposed improvements aim at decreasing the size of the switching table. This can be achieved by eliminating some of the redundant and idle entries, which also generate performance degradation and area overhead increase. Also we present a comparative analysis for the SAM method with and without the improvements proposed, in regard to reduction of the overhead and increase in speed. The simulation results have shown that the number of entries in the switching table can be reduced up to 68%. Also we have shown by simulations that we can reduce the time penalty with up to over 80%.

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Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling

Abstract: Abstract-this paper proposes a novel Process Variation

Cited by 19 publications

References 13 publications

Software Controlled Memories for Scalable Many-Core Architectures

Software Controlled Memories for Scalable Many-Core Architectures

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Improving performance and area overhead by reducing the switching table for Self Adaptive cache Memories

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