Software Controlled Memories for Scalable Many-Core Architectures

Abstract

Technology scaling along with the ever evolving demand for media-rich software stacks have motivated the need for many-core platforms. With the increase in compute power and its inherent demand for high memory bandwidth comes the need for vast amounts of on-chip memory space. Thus, designers must carefully provision the memory real-estate to meet their application's needs. It has been shown in the embedded systems domain that both software controlled memories (e.g., scratchpad memories) and hardware-controlled memories (e.g., caches) have their pros and cons, some application domains such as multimedia fit very well in the software-controlled memory model, while other domains such as databases work well with caches. As a result, efficient memory management is extremely critical as it has a great impact on the system's power consumption and throughput. Traditional memory hierarchies primarily consist of SRAM-based onchip caches, however, with the emergence of non-volatile memories (NVMs) and mixed-criticality systems, on-chip memories will be heterogeneous, not only in type (cache vs. scratchpad) but also in technology (e.g., SRAM vs. NVM). This paper surveys the state of the art in memory subsystems for many-core platforms, and presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the various challenges designers face in deploying such memory subsystems (e.g., sharing the memory resources, accounting for variations in the subsystem, etc.).

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

“…memory interference) between different cores critically undermines the overall real-time system predictability, and therefore impacts even more its performance [38]. Large inter-task interferences due to increased resource sharing on multi-core platforms have severely undermined the predictability of real-time systems [39,40]. An increase of 300% has been seen in the estimated values of WCET of real-time tasks, when memory interferences are taken into consideration [41], which can lead to extremely pessimistic designs.…”

“…The large inter-task interferences due to increased resource sharing (such as shared buses and memory) on multi-core platforms have severely undermined the predictability of realtime systems [39,40]. For the sake of scalability, exibility, and to deal with power limitation in the era of dark silicon, it has become mainstream to group multiple cores sharing a local cache memory [160] [161] [162].…”

Modeling and mitigation of parametric time-dependent variability in digital systems

“…The concept is illustrated for two execution nodes and their kernels [230]. SW-controlled [22,47], to enable demand-driven rollbacks. Thus, the proposed methodology is hybrid (HW-SW) in nature, since the detection occurs in HW and the mitigation is initiated by SW. A timing penalty is paid only when errors do occur and can be reclaimed if appropriate utilities are available on the target platform (e.g.…”