Improving performance and area overhead by reducing the switching table for Self Adaptive cache Memories

Abstract

This paper proposes a number of improvements for the switching table used by the Self Adaptive cache Memories (SAM) method, as described in [1]. The Switching Table is used for maintaining performance in a continuously degrading memory. The proposed improvements aim at decreasing the size of the switching table. This can be achieved by eliminating some of the redundant and idle entries, which also generate performance degradation and area overhead increase. Also we present a comparative analysis for the SAM method with and without the improvements proposed, in regard to reduction of the overhead and increase in speed. The simulation results have shown that the number of entries in the switching table can be reduced up to 68%. Also we have shown by simulations that we can reduce the time penalty with up to over 80%.