BIST and production testing of ADCs using imprecise stimulus

Parthasarathy, K.L.; Kuyel, T.; Price, D.L.; Jin, Le; Chen, Degang; Geiger, R.L.

doi:10.1145/944027.944035

Cited by 18 publications

(9 citation statements)

References 9 publications

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“…A new approach to accurately testing an ADC in a production or BIST environment with dramatically reduced accuracy requirements on the test signal generator was recently introduced [3], [12]- [14]. With this approach, signal-processing techniques are used to accurately extract performance characteristics of the DUT that are embedded in output test data generated with low-accuracy signal generators.…”

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

“…The mathematics behind linearity testing of ADCs using nonlinear test signals unknown to the test algorithm is presented in [13], where a nonlinear stationary excitation and a level-shifted version of the nonlinear excitation are used as inputs to the DUT. Simulations and experimental results were used to validate this approach [13], [14].…”

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

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A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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Abstract-Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of Σ−∆ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digitalto-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and timelocal nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.Index Terms-Analog-to-digital converter (ADC) testing, built-in self-test (BIST), dynamic element matching (DEM), integral nonlinearity (INL) testing.

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Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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“…Firstly, a 1-bit Digital-to-Analog Converter (DAC) is needed to apply the stimulus to an analog block. This converter has to be 2 or 3 bits more precise than the Circuit Under Test (CUT) [12]. Any noise Paper 32.1…”

Section: Introductionmentioning

confidence: 99%

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

Rolindez

Mir

Carbonero

et al. 2007

2007 IEEE International Test Conference

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In this paper we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-In Self-Test (BIST) technique for the test of the Signal-to-Noise and Distortion Ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sinewave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 µm CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB. IntroductionIn order to satisfy the rising demand for high quality audio devices, the performances of Sigma-Delta Analog-toDigital Converters (Σ∆ ADCs) are continuously improving with larger modulator bandwidths and higher dynamic ranges. As the performances of these circuits increase, its test is in turn more difficult and costly. Built-In Self-Test (BIST) techniques can reduce this cost by integrating the test approach in the design phase.In the last years, an intense research effort has been carried out in order to find BIST solutions for ADCs. The Oscillation-based Built-In Self-Test (OBIST) was proposed in [1] for the calculation of the input transition voltages and non-linearity errors. The main advantage of this method is that we do not need to generate an analog input stimulus for the test. However, it does not measure dynamic parameters and it takes a long test time for high-resolution converters. The oscillation-based BIST has also been applied to the test of Σ∆ modulators [2], where the modulator is reconfigured to be an oscillator. Both the frequency and the amplitude of the oscillation are measured in order to separate faulty-circuits from faultfree ones. The need to modify the circuit and the sensibility to process variations can deteriorate the quality of this BIST approach.Other authors [3,4,5,6] have proposed the estimation of the leakage in the modulator integrators, which is directly related to the quantization noise present in the bandwidth of the modulator at its output. Additionally, the same approach is used in [6] for the estimation of the settlingtime. These approaches do not allow for a complete validation of the modulator and additional tests may be necessary. Furthermore, in [3] and [4] large digital resources are required.The histogram-based technique has also been applied to the BIST of ADCs in [7]. However, only static information is obtained and long test times are necessary when the number of ...

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“…Forth, the test circuit should be able to measure/test the desired specifications of the circuit under test (CUT), which may vary with respect to the application domain. Generally, BiST techniques for mixed-signal circuits have been targeted at specific parameters of specific mixedsignal circuits, such as the DNL of a data converter, or the jitter of a PLL [8,11,17,16,7,1].…”

Section: Introductionmentioning

confidence: 99%

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise

Erdogan

Ozev

2006

2006 IEEE International Test Conference

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As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters ofanalog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation ofmeasured specs. In this paper, we propose a builtin test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, lowfrequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8um CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specifiedfail level.

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BIST and production testing of ADCs using imprecise stimulus

Cited by 18 publications

References 9 publications

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise

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BIST and production testing of ADCs using imprecise stimulus

Cited by 18 publications

References 9 publications

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

A stereo audio &#x03A3;&#x2211; ADC architecture with embedded SNDR self-test

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise

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A stereo audio Σ∑ ADC architecture with embedded SNDR self-test