A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogrambased algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.
This paper describes the technique of two-phase decimation. When combined with the previously known technique of jitter compensation, it allows the performance of the echo canceler in a full-duplex data transceiver to be preserved in the presence of both the phase steps generated by the timing recovery digital phase locked loop and rapid changes in the sampling phase of the input signal. This results from being able to train the jitter canceler continuously, instead of restricting the training to some initial startup period. Moreover, this technique provides an efficient way to preserve the time invariance of the echo path during a phase step, a precondition for the jitter compensation technique to perform properly.
Architectural and circuit innovations resulting in a 260mW single-chip ISDN U-interface transceiver wii h a range of more than 21Kft of AWG26 cable are described. These include a new scheme for jitter compensation using a two-phase decimator that results in faster phase adjustment and jitter tracking, and a fastconverging nonlinear echo canceler that can track time-dependent components of nonlinear distortion.
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