An ANSI standard ISDN transceiver chip set

Khorramabadi, H.; Agazzi, O.E.; Koh, Taiho; Haider, Syed S.; Anidjar, J.; Cassiday, D.R.; Daubert, S.J.; Gerveshi, C.M.; Kumar, Suresh; Lalumia, Mariano; Ollo, S.; Peterson, T.R.; Price, D.L.; Tracy, P.H.; Walden, R. W.; Wilson, Gordon; Dwarakanath, M.R.; Kumar, Jayant; Shaw, R.F.; Wilson, Robert A.; Gottfried, N.L.; Heiskanen, M.L.; McDonald, W.R.; Ramesh, N.S.; Blake, R.B.

doi:10.1109/isscc.1989.48279

Cited by 8 publications

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“…Output from the last PE is summarized. While the main focus of this paper is on the fed back to the first one with a proper delay while the update signal processor, a companion analog chip [2] in the transceiver signal is rotated K times through the PE's. Each PE now needs performs certain front-end processing.…”

Section: Linear Echo Cancelercec)mentioning

confidence: 99%

Algorithms and architecture of a VLSI signal processor for ANSI standard ISDN transceiver

Koh

Agazzi

Haider

et al.

International Conference on Acoustics, Speech, and Signal Processing

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summarized below. The transmitter is entirely an analog implementation, except for scrambling. It consists of a D/A We have developed a VLSI signal processor for ISDN Uconverter and a second-order Butterworth filter, followed by a interface transceivers conforming to the new ANSI standard.l i e driver which feeds line pulses to the hybrid. AIDThe standard employs the 2 8 1 4 line code in which four-level conversion at the receiver is done by a sigma delta modulator symbols are transmitted in both directions at a rate of 80,ooO with a double integration loop. which places the quantization bauddsec. This paper will describe algorithms and architecture noise at high frequencies mostly outside the baseband [31. used in the processor. DECIMATOR (DEC)

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Section: Linear Echo Cancelercec)mentioning

confidence: 99%