A CMOS line driver with 80-dB linearity for ISDN applications

Khorramabadi, H.

doi:10.1109/4.126541

Cited by 37 publications

(16 citation statements)

References 4 publications

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“…Meanwhile, line driver circuits are used as power amplifiers in wireless communication systems. In fact, this element is an interface buffer which provides necessary current to drive the small load impedance, which is nominally between 50 and 150-Q [1] and varies upon the cable length, temperature, tolerances of fabrication process, and other external effects. Therefore, line driver must be able to compensate load's variations by tuning and matching of output impedance otherwise reflections are not canceled at the transmitter end, which degrades the driver performance.…”

Section: Introductionmentioning

confidence: 99%

“…An ISDN line driver [1] has been designed with 80-dB linearity and 2.5-Vp-p swing. Using a fully differential structure with tuning [3] achieves better than 47-dB linearity with a 75-Q load.…”

Section: Introductionmentioning

confidence: 99%

“…Low dc gain error amplifier causes error in signal voltage when copied from input node to Vx and then to the output node. On the other hand, high gain error amplifier causes large variation in quiescent current from its preset value in the existence of offset voltage and mismatching [1]. Obviously, using of variable gain error amplifier, which is low gain in quiescent state and high gain in driving mode, circumvents the problem [4].…”

Section: Introductionmentioning

confidence: 99%

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An Adaptive Low Power Video Line Driver

Askarpour¹

2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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In this paper an adaptive line driver for 2.5V power supply designed in standard 0.25jm CMOS technology is presented. This line driver delivers 2-Vp-p on transmission lines with 100Q characteristics impedance. Achieving total harmonic distortion is 41-dB for a 5MHz, 2-Vp-p input signal. Variable gain error amplifiers have been employed for quiescent current stability, also tuning module of this configuration is totally implemented by active elements. This structure compensates 30% variation of load impedance and consumes approximately 3.5-mW static power at 100Q.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Adaptive Low Power Video Line Driver

Askarpour¹

2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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“…3 as an output buffer for large signaling and low output impedance [4], [5]. When a current-steering DAC is employed for a multi-level application, a pseudo-source amplifier requires a current-to-voltage converter, generally implemented as a pre-amplifier.…”

Section: Voltage-mode Drivermentioning

confidence: 99%

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

Park¹,

Lee²,

Jeong³

2007

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies 0.14 mm 2 . Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

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“…Thus the power dissipation of the column driver is dependent on the image display [13]. In this paper we apply a reduction technique on the proposed circuit to reduced the size and getting a better power efficiency [14][15]. A variable bias current was used to reduce the power dissipation.…”

Section: Introductionmentioning

confidence: 99%

A High Slew Rate Buffer Amplifier Employing MTCMOS Technique for Flat Panel Display

Yadav¹,

Khandelwal²,

Akashe³

2014

IJCA

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This paper address a low power, high speed class AB buffer amplifier topology for liquid crystal display applications which offer a rail to rail common mode input range. The presented circuit use two comparator circuit inside it to enhance the slewing capabilities with a limited power consumption and it draw a very small quiescent current during static operation for rail to rail common mode input range. The circuit describes here the capacitive load behaviour with reduced distortion at the output node for swing characteristics. By applying MTCMOS (Multi threshold CMOS) reduction technique leakage current is reduced from 56nA to 52nA, power is reduced from 377.3 pW to 221pW, reduced slew rate and tranconductance of 4.363. A buffer circuit can run 1nF of load capacitance of achieving a rise time 800E-12, duty cycle is 4.5, Average group delay is 221E-3, unity gain frequency is 221.7E-3 and harmonic frequency is 1.532 at 20 Hz. The circuit has been demonstrated at 45 nm technology.

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A CMOS line driver with 80-dB linearity for ISDN applications

Cited by 37 publications

References 4 publications

An Adaptive Low Power Video Line Driver

An Adaptive Low Power Video Line Driver

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

A High Slew Rate Buffer Amplifier Employing MTCMOS Technique for Flat Panel Display

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