Algorithms and architecture of a VLSI signal processor for ANSI standard ISDN transceiver

Abstract

summarized below. The transmitter is entirely an analog implementation, except for scrambling. It consists of a D/A We have developed a VLSI signal processor for ISDN Uconverter and a second-order Butterworth filter, followed by a interface transceivers conforming to the new ANSI standard.l i e driver which feeds line pulses to the hybrid. AIDThe standard employs the 2 8 1 4 line code in which four-level conversion at the receiver is done by a sigma delta modulator symbols are transmitted in both directions at a rate of 80,ooO with a double integration loop. which places the quantization bauddsec. This paper will describe algorithms and architecture noise at high frequencies mostly outside the baseband [31. used in the processor. DECIMATOR (DEC)