A digital signal processor for an ANSI standard ISDN transceiver

Agazzi, O.E.; Koh, Taiho; Haider, Syed S.; Walden, R. W.; Cassiday, D.R.; Wilson, Gordon; Lalumia, T.M.; Gerveshi, C.M.; Kumar, Jayant; Crochiere, R.; Shaw, R.F.; Wilson, Robert A.; McDonald, W.R.; Gottfried, N.L.; Ramesh, N.S.; Blake, R.B.

doi:10.1109/4.44996

Cited by 16 publications

(4 citation statements)

References 25 publications

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“…The use of the design methodology described in [6] resulted once again in fully functional first silicon. Fig.…”

Section: Expe:rimental Results and Conclusionmentioning

confidence: 99%

“…It imposes heavy loading on the transmitter and large echo conditions. Most transceivers would fail to start on this loop ( [6] is an exception). The transceiver described here starts every time and it operates with high SNR on this and other similar loops.…”

Section: Expe:rimental Results and Conclusionmentioning

confidence: 99%

“…It consists of a test control input, used to load a test instruction serially on a 49-bit test instruction register, a test data input to provide stimulus for the blocks under test, and a test data output through which the chip responses are observed. The test modes described in [6], and new modes that enhance the testability of the analog circuits and the DPLL are supported. In addition, the loopback and echo canceler residue tests can be initiated from the system interface.…”

Section: Test Architecturementioning

confidence: 99%

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A Single-chip Ansi Standard Isdn U-interface Transceiver

Agazzi¹,

Khorramabadi²,

Anidjar³

et al.

Proceedings of the IEEE Custom Integrated Circuits Conference

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Architectural and circuit innovations resulting in a 260mW single-chip ISDN U-interface transceiver wii h a range of more than 21Kft of AWG26 cable are described. These include a new scheme for jitter compensation using a two-phase decimator that results in faster phase adjustment and jitter tracking, and a fastconverging nonlinear echo canceler that can track time-dependent components of nonlinear distortion.

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“…The use of the design methodology described in [6] resulted once again in fully functional first silicon. Fig.…”

Section: Expe:rimental Results and Conclusionmentioning

confidence: 99%

Section: Expe:rimental Results and Conclusionmentioning

confidence: 99%

Section: Test Architecturementioning

confidence: 99%

See 1 more Smart Citation

A Single-chip Ansi Standard Isdn U-interface Transceiver

Agazzi¹,

Khorramabadi²,

Anidjar³

et al.

Proceedings of the IEEE Custom Integrated Circuits Conference

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show abstract

“…The system design of conventional transceivers has been extensively discussed in the literature [1][2][3][4][5][6].…”

Section: List Of Figuresmentioning

confidence: 99%

Design of CMOS decision feedback equalizer for high speed backplane transceiver

Chen¹

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The ISDN U interface and transceiver

Borns

1991

Int. J. Satell. Commun.

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This paper describes the integrated services digital network (ISDN) basic rate interface (BRI) two‐wire U interface and the transceiver necessary for the digital transmission of 160 kb/s of information over unshielded twisted pair transmission media. Topics discussed include the U interface structure and framing as described in the American National Standards Institute (ANSI) T1.601 specification, and the VLSI implementation of the ISDN U transceiver. Pertinent transceiver design issues addressed include the type of line code used, such as 2B1Q or 4B3T, echo cancellation, near end crosstalk, equalization and sampling rates.

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A digital signal processor for an ANSI standard ISDN transceiver

Cited by 16 publications

References 25 publications

A Single-chip Ansi Standard Isdn U-interface Transceiver

A Single-chip Ansi Standard Isdn U-interface Transceiver

Design of CMOS decision feedback equalizer for high speed backplane transceiver

The ISDN U interface and transceiver

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