A high-linearity 50- Omega CMOS differential driver for ISDN applications

Castello, R.; Nicollini, G.; Monguzzi, P.

doi:10.1109/4.104172

Cited by 23 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A third p.ossible technique t.o c.ontr.ol the quiescent level in a push-pull stage is the use .of "quasi current mirr.ors" in front .of the .output devices [11,12,13]. This technique is sh.own c.onceptually in Fig.9 with reference t.o the p side .of the push-pull circuit.…”

Section: M2mentioning

confidence: 97%

CMOS Buffer Amplifiers

Castello

1993

Analog Circuit Design

View full text Add to dashboard Cite

This paper gives a tutorial presentation on the design of buffer amplifiers in CMOS technology. These are circuits that must drive a load made up of either a large capacitor or a small resistor or both. The core of the paper deals with special purpose buffer amplifiers intended for a specific application most often within a mixed analOg/digital system integrated on a single chip. Several architectures for both input class NB and output push-pull stages are discussed and compared. Issues like quiescent current control, frequency compensation, open loop and closed loop linearity are analysed in detail with the help of many examples.

show abstract

Section: M2mentioning

confidence: 97%

CMOS Buffer Amplifiers

Castello

1993

Analog Circuit Design

View full text Add to dashboard Cite

show abstract

“…Indeed the stability of NMC amplifier (or SMC amplifier) is always improved when the output stage transconductance is increased, therefore making it very suitable compensation technique for power amplifiers. Some of those amplifiers which have used NMC, or NMC with Ahuja-type [14] inner compensation loop, have driven the output stage from a variable impedance node, which has low impedance characteristics for small signals, but high impedance characteristics when the output stage is driven hard [15][16][17]. Although in this way stability and rail-to-rail drive of the output stage are assured, bandwidth for small signals is reduced, because when the impedance of the node is low SMC or its derivatives would be sufficient to stabilize the amplifier.…”

Section: Introductionmentioning

confidence: 99%

Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

Loikkanen

Kostamovaara

2006

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper describes a CMOS power amplifier with rail-to-rail input and output, also suitable for low voltage applications. The amplifier uses Simple Miller Compensation with high bandwidth stage to robustly and power efficiently compensate the amplifier. Circuit also includes a common mode adapter block, based on resistive level shift network, to implement rail-to-rail input and optional adaptive biasing block, which can be used to extend bandwidth of the amplifier for large high frequency inputs in continuous-time applications. Measurement results show that the amplifier is capable of driving heavy resistive and capacitive loads having maximum output current exceeding 100 mA, when driving 1 nF 10 load from 3.0 V supply. Without adaptive biasing the linear amplifier achieves 5.7 MHz unity gain frequency and 61 • phase margin when driving 1 nF 1 k load, while drawing 2.4 mA from 1.5 V supply.

show abstract

Operational Amplifiers II

Baker¹

2010

Cmos

View full text Add to dashboard Cite

A high-linearity 50- Omega CMOS differential driver for ISDN applications

Cited by 23 publications

References 9 publications

CMOS Buffer Amplifiers

CMOS Buffer Amplifiers

Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

Operational Amplifiers II

Contact Info

Product

Resources

About