This paper describes the technique of two-phase decimation. When combined with the previously known technique of jitter compensation, it allows the performance of the echo canceler in a full-duplex data transceiver to be preserved in the presence of both the phase steps generated by the timing recovery digital phase locked loop and rapid changes in the sampling phase of the input signal. This results from being able to train the jitter canceler continuously, instead of restricting the training to some initial startup period. Moreover, this technique provides an efficient way to preserve the time invariance of the echo path during a phase step, a precondition for the jitter compensation technique to perform properly.
AN ARCIIITECTIJREthe Graph Search Machine (GSYI)designed to perform searching 0 1 graph-like data stnrcturcs will bc discussed. Whereas the conventional Digital Signal Processor (IISP), whose central hardware core is a multipleaccumulate pipeline optimized to execute the lcerncls of such operations as filtering, signal conditioning, and spcctral analysis, thc GSM is optimized to execu te the kernels of such algorithms as dynamic programming, syntactic analysis, and similarity measure. These operations are o f fundamental importance in speech recognition', image processing'. an(! artificial intelligence. m r~l c lcernel commonly used in spcech rccognition algorithms is a minirnum-accumulate type operation; Table 1. The GSM architecture exploits the central thcme of these algorithms. The main feature of the processor is the minimum-accumulate pipelinc also capable of computing the difference-magnitude-accumulate frrnction. .An additional processing element is parallel with the main pipcline gcncrates traceback information for word connectivity.The processor architecture is partitioned into six l'unction:ll lolocks consisting of a 16b dah-path, on chip instruction cachc and ROYI. an instruction decoder, a control unit, timing and synchronization, and parallel I/O ports; Figure 1. Key elements of thc data-path (DPA4TII) are a configurable stack and arithmetic unit (AU), a minimum selector (YTIN). an argument stack and counter (ARGRIIN), and a data-address generator (DAG). A total of 17 data registers is contained within the DPA'I'I-I and is implemented with a static master and dynamic slave section.A feed-forward and feedback path between the AU and RIN allow the DPATII to implement thc most constraining kernel found in Table 7 , an add-min-add operation (HMM entry).The AU performs both additions and subtractions, and generates overflow and sigp I'1;q;s. A minimum select or magnitude-accumulate is performed by the RIIN, the latter being uscd for L1 distance calculations. %IN flags indicate which input is a minimum and when both inputs are equal. The YlTN also signals a transfer of com,panion data such as pointers and indices from the L-stack and counter to holding registers for use in word reconstruction. The DAG calculates address displacemcnts for data in local memory and indicates that a predetermined address 'Bridle, J.S., Brown, E.'.L\., 2nd Gamherlain. R M., 'An Algorithm for Connected WorC Pecognition". Proc. i C A S S P p . 899-902; 1982. Configurations", I R E Trans. Electronic Ccmputers, 1'01. EC-10 'Freeman, H., "On the Ercecriing of Arbitrary Geometric p. 260-268; June, 1961. 3 Uya, M., Kaeko, K., Yasui, J.: "A CMOS Floating Point Multiplier", ISSCC DIGEST OF TECHNICAL P A P E R S p. 90.. 91; Feh., 1984.limit has l m n matched. A 2's complement saturating carry select adder3 was used to design the AU, WIN, anti DAG. The instruction cache, implemcnted as a RAM and ltOM both contain 32 words x 3% each. The cache size accommodates a variety o f tight inner-loops found in many application programs. In additio...
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