Abstract-Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of 2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability. Index Terms-Analog-to-digital converters (ADCs), integral nonlinearity (INL), linearity test, stimulus error identification and removal (SEIR).I. BACKGROUND T HE "histogram method" is a standard approach for quasi-static linearity testing of analog-to-digital converters (ADCs) [1]- [3]. However, during the past decade, linearity testing of ADCs has not received much research attention for several reasons. As long as best practices are followed, modern mixed-signal automated test equipment (ATE) can be used to make quasi-static linearity testing of ADCs a fairly straightforward production task for low-to-medium resolution ADCs [4]. High-precision delta-sigma ADCs are inherently sufficiently linear and do not require linearity testing. In the communications circuit area, high-speed pipelined ADCs are widely used and are usually production tested with high-frequency input signals [2], whereas quasi-static linearity testing is primarily used for debugging [5] or calibration [6]. Probably the biggest reason, however, can be attributed to the challenges associated with generating highly linear or spectrally pure test signals with no major technological breakthroughs occurring in this area in the past decade. Nevertheless, quasi-static linearity testing remains a test challenge for the production of certain classes of high performance ADCs, and the increasing downward production cost pressures are making the convenient use of expensive mixed-signal ATEs for testing low and medium resolution ADCs more difficult to justify. In this paper, emphasis ...
This paper is a detailed overview of the practical issues related to linearity testing of analog to digital converters. The focus is on the available technology and methods for ADC linearity testing, and the goal is to demonstrate the issues and problems effecting the test capability. Delta-Sigma DACs and LC filtered RF Frequency synthesizers are covered as linear sources for the ADCs. Histogram based ramp and sine wave methods are covered as linearity test techniques. Integral non-linearity (INL) plots from a 10-bit 2OMSPS pipeline ADC are given to demonstrate the test problems and performance. This work attempts to close the gap between the general theory and actual implementation problems of linearity tests for high performance ADCs.
Current digital image/video storage, transmission and display technologies use uniformly sampled images. On the other hand, the human retina has a nonuniform sampling density that decreases dramatically as the solid angle from the visual fixation axis increases. Therefore, there is sampling mismatch between the uniformly sampled digital images and the retina. This paper introduces Retinally Reconstructed Images (RRIs), a novel representation of digital images, that enables a resolution match with the human retina. To create an RRI, the size of the input image, the viewing distance and the fixation point should be known. In the RRI coding phase, we compute the 'Retinal Codes', which consist of the retinal sampling locations onto which the input image projects, together with the retinal outputs at these locations. In the decoding phase, we use the backprojection of the Retinal Codes onto the input image grid as B-Spline control coefficients, in order to construct a 3-D B-spline surface with nonuniform resolution properties. An RRI is then created by mapping the B-spline surface onto a uniform grid, using triangulation. Transmitting or storing the 'Retinal Codes' instead of the full resolution images enables up to two orders of magnitude data compression, depending on the resolution of the input image, the size of the input image and the viewing distance. The data reduction capability of Retinal Codes and RRI is promising for digital video storage and transmission applications.However, the computational burden can be substantial in the decoding phase.
A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogrambased algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.
TX capacitor mismatch is a major factor limiting high-resolution AUCs. A number of traditional techniques to ovemme this limitation are outlined in Table 8.6.1, along with the proposcd DAC and feedback capacitor averaging (DFCA) technique and mismatch noise cancellation (MNC) technique.DFCA simultaneously shuffles both the DAC and the feedback capacitors, resulting in high SFDR. Figure 8.6.1 shows the overall ADC architecture for chip I (DFCA) and chip I1 (DFCA + MNCI. Stages 1-5 are 3b/stage, followed by stage 6, which is a 4b flash ADC. The choice of 3blstage is a tradeoff between power consumption, conversion speed, and circuit complexity. Shufiling is applied to stages 1-3. The resulting broadband noise from shuffling can be cancelled using MNC, employing CDMA-like concepts Ill. MNC differs from the DAC Noise Cancellation 1 2 1 in that both DAC and interstage gain errors are cancelled. To cancel the mismatch noise from stage 1, MNC takes the 1Zh error-correctod outputs from stages 2~6, estimates and eancols the capacitor mismatch in the background and combines with the raw 3h from stage 1 to produce the final 14b.In conventional dynamic element matching (DEM) techniques, themometer codes are shuffled in digital domain after the latches. When applied to a pipelined ADC, this implies an increase of the non-overlapping period of the clock, limiting the ADC conversion speed. Figure 8.6.2 shows tho DFCA implemented. Shufiling occurs in the analog domain before the latches. Theanan-overlapping time can therefore be reduced to accommodate only the simple capacitor switch logic (CSLI. Unlike DEM in U converters, where mismatch noise shaped spectrum limits the input signal bandwidth to a fraction of the Nyquist rate, DFCA achieves high SFDR while remaining compatihlc with broadband Nyquist-rate ADCs.In addition, DFCA removes interstage gain error due to capacitor mismatch, while XA DEM removes only DAC errors. DFCA-MNC comhination acts as background calibration by continuously canceling out capacitor mismatch. Previous background calibration techniques address only DAC errors 121 or interstage gain error 131, and can require extra analog components 141. The DFCA-MNC combination is free of these drawbacks.Each pipeline stage uses four capacitors on each side of the fully differential ADC. The stage is configured in the amplification phase in Figure 8.6.2a. Since the total number of capacitors including the feedback capacitor is a power of two, DFCA implementation is simple. At any given clock cycle, one of four capacitors is randomly selected as the feedback capacitor, while the remaining three DAC capacitors arc shumed simultaneously.In Figure 8.6.2h, one side of the fully differential parallel shuffling networks (PSN) is shown. The inputs to the shuffling networks are analog signals representing 2b codes alaO, blbO, clc0, and flm. Since the feedback capacitors arc shumed along with the DAC capacitors, the bottom plate of each capacitor can have one of four connections: VREF+, VCM, VREF~, and Vom of the opamp. The cod...
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