TX capacitor mismatch is a major factor limiting high-resolution AUCs. A number of traditional techniques to ovemme this limitation are outlined in Table 8.6.1, along with the proposcd DAC and feedback capacitor averaging (DFCA) technique and mismatch noise cancellation (MNC) technique.DFCA simultaneously shuffles both the DAC and the feedback capacitors, resulting in high SFDR. Figure 8.6.1 shows the overall ADC architecture for chip I (DFCA) and chip I1 (DFCA + MNCI. Stages 1-5 are 3b/stage, followed by stage 6, which is a 4b flash ADC. The choice of 3blstage is a tradeoff between power consumption, conversion speed, and circuit complexity. Shufiling is applied to stages 1-3. The resulting broadband noise from shuffling can be cancelled using MNC, employing CDMA-like concepts Ill. MNC differs from the DAC Noise Cancellation 1 2 1 in that both DAC and interstage gain errors are cancelled. To cancel the mismatch noise from stage 1, MNC takes the 1Zh error-correctod outputs from stages 2~6, estimates and eancols the capacitor mismatch in the background and combines with the raw 3h from stage 1 to produce the final 14b.In conventional dynamic element matching (DEM) techniques, themometer codes are shuffled in digital domain after the latches. When applied to a pipelined ADC, this implies an increase of the non-overlapping period of the clock, limiting the ADC conversion speed. Figure 8.6.2 shows tho DFCA implemented. Shufiling occurs in the analog domain before the latches. Theanan-overlapping time can therefore be reduced to accommodate only the simple capacitor switch logic (CSLI. Unlike DEM in U converters, where mismatch noise shaped spectrum limits the input signal bandwidth to a fraction of the Nyquist rate, DFCA achieves high SFDR while remaining compatihlc with broadband Nyquist-rate ADCs.In addition, DFCA removes interstage gain error due to capacitor mismatch, while XA DEM removes only DAC errors. DFCA-MNC comhination acts as background calibration by continuously canceling out capacitor mismatch. Previous background calibration techniques address only DAC errors 121 or interstage gain error 131, and can require extra analog components 141. The DFCA-MNC combination is free of these drawbacks.Each pipeline stage uses four capacitors on each side of the fully differential ADC. The stage is configured in the amplification phase in Figure 8.6.2a. Since the total number of capacitors including the feedback capacitor is a power of two, DFCA implementation is simple. At any given clock cycle, one of four capacitors is randomly selected as the feedback capacitor, while the remaining three DAC capacitors arc shumed simultaneously.In Figure 8.6.2h, one side of the fully differential parallel shuffling networks (PSN) is shown. The inputs to the shuffling networks are analog signals representing 2b codes alaO, blbO, clc0, and flm. Since the feedback capacitors arc shumed along with the DAC capacitors, the bottom plate of each capacitor can have one of four connections: VREF+, VCM, VREF~, and Vom of the opamp. The cod...
Flexible AC Transmission Systems (FACTS) have been proposed in the late 1980s to meet and provide the electrical power system requirements. FACTS are used to control the power flow and to improve the power system stability. Interline power flow controller (IPFC) is a versatile device in the FACTS family of controllers and one of its latest generations which has the ability to simultaneously control the power flow in two or multiple transmission lines. This paper is tackling the IPFC performance in power systems; it aims to discuss the availability to define a known scenario for the IPFC performance in different systems. An introduction supported with brief review on IPFC, IPFC principle of operation and IPFC mathematical model are also introduced. IEEE 14-bus and 30-bus systems have chosen as a test power systems to support the behavior study of power system equipped with IPFC device. Three different locations have chosen to give variety of system configurations to give effective performance analysis.
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