A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Abstract

Abstract-Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of Σ−∆ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digitalto-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and timelocal nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.Index Terms-Analog-to-digital converter (ADC) testing, built-in self-test (BIST), dynamic element matching (DEM), integral nonlinearity (INL) testing.

Design of an on-chip stepwise ramp generator for ADC static BIST applications

“…The approach in [6], [7] is aimed at relaxing the linearity requirements on the ramp generator. It proposes to use of a low resolution DAC with redundant, poorly matched elements together with a Deterministic Dynamic Element Matching (DDEM) strategy in order to estimate the static characteristics of a high resolution ADC.…”

“…It proposes to use of a low resolution DAC with redundant, poorly matched elements together with a Deterministic Dynamic Element Matching (DDEM) strategy in order to estimate the static characteristics of a high resolution ADC. The work in [6], [7] demonstrates that a DDEM 8-bit DAC can be used to test a 12-bit ADC.…”

Deterministic DEM DAC Performance Analysis

“…This analysis answers the question why low resolution/linearity DACs with DDEM control can be used for high resolution ADC static linearity test. In [5], attempt was made to evaluate the performance for a given DDEM DAC quantitatively. A formula was given to predict the equivalent linearity of a DDEM DAC as ADC static linearity test stimulus source.…”

Fully digital-compatible built-in self-test solutions to linearity testing of embedded mixed-signal functions

“…The four start points selected are i 1 , i 5 , i 9 , and i 13 . In the previous research, the DDEM-incorporated DACs are used as source generators, producing discrete stimulus samples for ADC histogram testing [28] [29] [35].…”

“…This is a promising solution to BIST source signal generation; however, the post digital processing needs a complex DSP block. Another approach to reduce the complexity of on-chip source generator is to use lowaccuracy, current-steering DACs incorporated with a so-called deterministic dynamic element matching method (DDEM) [28] [29]. It has been proven that the resolution and linearity of overall output distribution can be improved by the reconfiguration method and that the proposed source generator can then be used in ADC histogram BIST for INL and DNL specifications.…”