An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Watanabe, Naoya; Morishita, Fukashi; Taito, Yasuhiko; Yamazaki, Akira; Tanizaki, T.; Dosaka, K.; Morooka, Y.; Igaue, F.; Furue, Katsuya; Nagura, Yoshihiro; Komoike, T.; Morihara, Toshinori; Hachisuka, A.; Arimoto, Kazutami; Ozaki, H.

doi:10.1109/isscc.2001.912686

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…To calculate the equivalent retention time for a target temperature, we first calculate the total amount of charge leaked from the storage capacitor during the retention-time specification at the reference temperature , i.e., 85 C. Then the leakage during the equivalent retention time at the target temperature has to be equivalent to , which is expressed in (14) (14) Therefore, the equivalent retention time at the target temperature can be obtained by (15) …”

Section: Analysis Of Equivalent Retention Timementioning

confidence: 99%

“…By reducing the tester requirement and enabling the parallel testing of different memory cores, memory built-in-self-test (BIST) circuit is the best solution to the embedded memory testing in common consensus today [9]- [11]. Several BIST schemes are proposed for the embedded DRAM testing [12]- [15]. However, these previous works mainly focus on the architecture and the automatic generation of the BIST circuitry.…”

Section: Introductionmentioning

confidence: 99%

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Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

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The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

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Section: Analysis Of Equivalent Retention Timementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…A more attractive solution to this test problem is the use of a built-in self-test (BIST) system that is adapted to provide all of the necessary elements required for high fault coverage on DRAM, including the calculation of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test mode application for margin testing [13,14]. The Cu-11 embedded DRAM macro has been developed around the idea of user simplicity, while including a high degree of flexibility, function, and performance [15].…”

Section: Embedded Dram Macro Design Considerationsmentioning

confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, highperformance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

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“…This pressure extends into testing, where use of traditional direct memory access (DMA) is costly in silicon area and wiring complexity, and introduces uncertainty in performance-critical tests. A more attractive solution to this test problem is the use of a built-in self-test (BIST) system that is adapted to provide all of the necessary elements required for high fault coverage on DRAM, including the calculation of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test-mode application for margin testing [4,5]. This paper presents an overview of the macro design, architecture, and BIST implementation as part of the IBM third-generation embedded DRAM for the IBM Blue Logic* 0.11-m ASIC design system (CU-11), offering a 4ϫ density advantage over SRAM.…”

Section: Introductionmentioning

confidence: 99%

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

et al. 2002

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This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic ® 0.11-m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM. the advent of embedded DRAM offerings in a logic-based ASIC technology [3], the performance of embedded DRAM macros has improved significantly over that of DRAM-based technologies. Users are increasingly replacing SRAM implementations with embedded DRAM,

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An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Cited by 8 publications

References 6 publications

Testing Methodology of Embedded DRAMs

Testing Methodology of Embedded DRAMs

Embedded DRAM: Technology platform for the Blue Gene/L chip

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

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