An efficient implementation of Boolean functions as self-timed circuits

David, I.; Ginosar, Ran; Yoeli, Michael

doi:10.1109/12.123377

Cited by 96 publications

(42 citation statements)

References 9 publications

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“…In each case, the 2NCL circuit has gate orphans. 4 More precisely, the functionality is equivalent after considering dual-rail encoding of the original gate. TABLE I.…”

Section: Theorem 1 (Input Completeness Relaxation) Let a 3ncl Circuitmentioning

confidence: 99%

“…Two strategies have been proposed: (i) optimizing every gate, but adding local completion detectors [1], [4], [10], and (ii) optimizing only some of the gates, with no added local completion detectors [16]. In the first strategy, all gates are relaxed to speed up computation, but local detectors are used to ensure robust completion.…”

Section: C-4mentioning

confidence: 99%

“…Given a 3NCL gate, a 3NCL-to-2NCL transformation of the gate is legal when (a) it has equivalent functionality to the 3NCL gate, 4 and (b) it is locally gate-orphan-free for all possible input transitions in the set and reset phases.…”

Section: Definitionmentioning

confidence: 99%

“…Basic design styles for this class of circuits have been proposed by several researchers: DIMS (Delay-Insensitive Minterm Synthesis) [15], [18], [4] and NCL (Null Convention Logic) [6]. The DIMS style is a simple approach to designing robust dual-rail asynchronous circuits from Boolean netlists in a template-based manner.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

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“…In each case, the 2NCL circuit has gate orphans. 4 More precisely, the functionality is equivalent after considering dual-rail encoding of the original gate. TABLE I.…”

Section: Theorem 1 (Input Completeness Relaxation) Let a 3ncl Circuitmentioning

confidence: 99%

Section: C-4mentioning

confidence: 99%

Section: Definitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…In case of [11], for the worst scenario of all the false outputs of a function block evaluating to a logic high when valid input data has been applied, all the sum terms of the monotonic subnet DRN would have become enabled. When spacer is applied, even with a single sum term becoming disabled, and with ORN and CEN being reset, all the false outputs may evaluate to the correct empty state.…”

Section: Previous Workmentioning

confidence: 99%