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Abstract

Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases.

A novel processing-in-storage (PRinS) architecture based on Resistive CAM (ReCAM) is described and proposed for Smith-Waterman (S-W) sequence alignment. The ReCAM PRinS massively-parallel compare operation finds matching base-pairs in a fixed number of cycles, regardless of sequence length. The ReCAM PRinS S-W algorithm is simulated and compared to FPGA, Xeon Phi and GPU-based implementations, show ing at least 4.7× higher throughput and at least 15× low er pow er dissipation.

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METASTABILITY EVENTS ARE common in digital circuits, and synchronizers are a necessity to protect us from their fatal effects. Originally, synchronizers were required when reading an asynchronous input (that is, an input not synchronized with the clock so that it might change exactly when sampled). Now, with multiple clock domains on the same chip, synchronizers are required when on-chip data crosses the clock domain boundaries. Any flip-flop can easily be made metastable. Toggle its data input simultaneously with the sampling edge of the clock, and you get metastability. One common way to demonstrate metastability is to supply two clocks that differ very slightly in frequency to the data and clock inputs. During every cycle, the relative time of the two signals changes a bit, and eventually they switch sufficiently close to each other, leading to metastability. This coincidence happens repeatedly, enabling demonstration of metastability with normal instruments. Understanding metastability and the correct design of synchronizers to prevent it is sometimes an art. Stories of malfunction and bad synchronizers are legion. Synchronizers cannot always be synthesized, they are hard to verify, and often what has been good in the past may be bad in the future. Papers, patents, and application notes giving wrong instructions are too numerous, as well as library elements and IP cores from reputable sources that might be ''unsafe at any speed.'' This article offers a glimpse into the theory and practice of metastability and synchronizers; the sidebar ''Literature Resources on Metastability'' provides a short list of resources where you can learn more about this subject.

Locally generated, arbitrated clocks for GALS SoCs [1] face the risk of synchronization failures if clock delays are not accounted for. The problem is analyzed based on clock delays, cycle times, and complexity of the asynchronous port controllers. A number of methods are presented. In some cases, it is sufficient to extract all the delays and verify whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, asynchronous synchronizers or matched-delay asynchronous ports may be employed. Arbitrated clocks may be traded off for locally delayed input and output ports, facilitating high data rates. The latter circuits have been simulated, to verify their performance.

Abstract-A mixed-signal front-end processor for multichannel neuronal recording is described. It receives twelve differential-input channels of implanted recording electrodes. A programmable cutoff HPF blocks DC and low frequency input drift at about 1Hz. The signals are band-split at about 200Hz to low-frequency local field potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmablecutoff LPF, in a range of 8-13kHz. Amplifier offsets are compensated by 5-bit calibration DACs. The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35µm CMOS process and tested successfully, demonstrating a 3µV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host.