QNoC: QoS architecture and design process for network on chip

Bolotin, Evgeny; Cidon, Israel; Ginosar, Ran; Kolodny, Avinoam

doi:10.1016/j.sysarc.2003.07.004

Cited by 450 publications

(301 citation statements)

References 16 publications

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“…Specifically, the connection path between the source and destination pair of GS packets is built at the time before they are injected onto the network [44][45][46][47][48][49][50][51]. However, this kind of static preallocation may result in high service latency and does not consider hotspots created by temporal shifts in data requirements, thus, leads to a rather unscalable NoC.…”

Section: Connection-oriented Schemementioning

confidence: 99%

“…The connection-less scheme is an alternative way to support different service levels in NoCs where the resource authorities are prioritized according to the QoS requirement of a traffic flow [48]. This is a distributed technique which allows traffic to be classified into different service levels.…”

Section: Connection-less Schemementioning

confidence: 99%

“…These service levels can often coincide with different virtual channels inside the switch. As two traffic flows with different QoS requirements are presented on the same channel simultaneously, the higher prioritized flow can interrupt the lower one and traverse this channel antecedently [48,52]. It is more adaptive to network traffic and potential hotspots and can better utilize the network.…”

Section: Connection-less Schemementioning

confidence: 99%

“…Furthermore, better bandwidth utilization and less hardware cost can be achieved since the traffic is allocated with network resources dynamically. With the consideration of performance requirements for each service level, a network designer can select an appropriate bandwidth implemented in an NoC to both meet the QoS constraints and save the wiring cost [48,54,55].…”

Section: Connection-less Schemementioning

confidence: 99%

See 3 more Smart Citations

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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Section: Connection-oriented Schemementioning

confidence: 99%

Section: Connection-less Schemementioning

confidence: 99%

Section: Connection-less Schemementioning

confidence: 99%

Section: Connection-less Schemementioning

confidence: 99%

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Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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“…Pareto dominance is used to compare and rank the mapping solutions. A mapping belongs to the Pareto optimal set if there is no other mapping that can improve at least one of the objectives without degrading any other objective (nondominance) [4][5][6]8]. Three multi-objective mapping strategies, PBBB, MGAP and multi-objective adaptive immune algorithm (MAIA) have been proposed to solve single application NoC mapping [4,5].…”

mentioning

confidence: 99%

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Sepulveda

Chau

Gogniat

et al. 2012

Analog Integr Circ Sig Process

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Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M 2 AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 wellknown benchmarks, including random and real applications, and combines up to 8 applications at the same SoC.The experimental results showed that the M 2 AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.

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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Sethi

Hussin

Hamid

2018

IEEJ Transactions Elec Engng

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Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

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QNoC: QoS architecture and design process for network on chip

Cited by 450 publications

References 16 publications

Networks on Chips: Structure and Design Methodologies

Networks on Chips: Structure and Design Methodologies

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

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