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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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An enhanced on-chip network resource allocation method is developed for the Bi-directional Network-on-Chip (BiNoC) platform. Specifically, a novel flow Fluidity Meter (FM) is proposed to provide the real-time estimate of bandwidth utilization of the Virtual Channel (VC) buffer in a BiNoC router.The degree of fluidity of a packet transfer in each router is a reliable, yet low-cost method for measuring bandwidth utilization in the VC. We show that the overhead implementing this FM is very affordable. Finally, extensive simulation results verify that this proposed FM approach achieves superior performance compared to existing BiNoC resource allocation methods.

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