A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

Lan, Ying-Cherng; Lin, Hsiao-An; Lo, Shih-Hsin; Hu, Yu; Chen, Sao-Jie

doi:10.1109/tcad.2010.2086930

Cited by 44 publications

(35 citation statements)

References 23 publications

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“…Al Faruque et al [7] apply centralized configuration on directions of 2X-Links to implement bidirectional transmission. Lan et al [8] propose selfreconfigurable bidirectional channels with direction control protocol to satisfy bandwidth requirement. Qian et al [9] further propose a flit-level speedup scheme by allowing flits of a packet to be transmitted in both inter-router channels simultaneously.…”

Section: Related Workmentioning

confidence: 99%

“…Fig. 6 compares the cycles consumed to send or fetch data streams using HyDMA and other DMA approaches based on various NoCs, including a conventional PS-NoC, a PS-NoC with two pairs of inter-router links (PS-NoC-2X) to provide better performance than BiNoC [8], and a CS-NoC with runtime configuration in a PS sub-network [13]. Considering the effect of routers' processing latency on the performance of DMA transfers, we also add HyDMA-SC and PS-NoC-SC using single-cycle routers to the performance comparison.…”

Section: Single Dma Transfermentioning

confidence: 99%

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HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

Wei

Liu

Sun

et al. 2016

IEICE Electron. Express

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With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packetcircuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.

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Section: Related Workmentioning

confidence: 99%

Section: Single Dma Transfermentioning

confidence: 99%

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

Wei

Liu

Sun

et al. 2016

IEICE Electron. Express

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show abstract

“…To realize a dynamically self-reconfigurable bidirectional channel NoC architecture, we initially modified the input/output port configuration and router control unit designs based on the conventional router using wormhole flow control as we proposed in [86]. In order to dynamically adjust the direction of each bidirectional channel at run time, we add a channel control module to arbitrate the authority of the channel direction as illustrated in Figure 9.…”

Section: The Proposed Binoc Router Designmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2012

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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“…Different OCI-based architectures using packet-switching have been recently studied and adapted for SoCs. Examples of these architectures and topology are Fat-Tree (FT) [2], 2D mesh [3], Ring [4], Butterfly-Fat Tree (BFT) [5], Torus [6], Spidergon [7], Octagon [8], WK-Recursive [9]. However, as the architecture is improved to enhance the performance of the system, their increasing complexity makes their design extremely challenging.…”

Section: Introductionmentioning

confidence: 99%

A New Methodology in Study of Effective Parameters in Network-on-Chip Interconnection’s (Wire/Wireless) Performance

Haghi¹,

Thurow²,

Stoll³

et al. 2016

ijacsa

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Abstract-Network-on-Chip (NoC) paradigm has been proposed as an alternative bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely considered. Time latency and throughput are two very critical parameters which play vital role to improve the system performance. In this work, these two elements are evaluated in both wire and wireless approaches under different conditions for networks contain 64,512 and 1024 number of cores. There are number of parameters those have direct and indirect effects on the delay and throughput, among all, these four are chosen: routing algorithm, buffer size, virtual channel and subnet. Thus this work is clustered into two general parts, in the first section the effect of algorithms and buffer size are calculated and then later on in second part when switching from wire approach to wireless, it's shown that, virtual channel and subnet are able to influence the performance of a network on chip positively under some circumstances. We don't concentrate on approach and techniques here. Our target in this paper is to determine the critical points, trade-off and study the effect of mentioned parameters on entire system. Evaluation is done by means of Booksim and Noxim simulators which are based on system C.

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A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

Cited by 44 publications

References 23 publications

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

Networks on Chips: Structure and Design Methodologies

A New Methodology in Study of Effective Parameters in Network-on-Chip Interconnection’s (Wire/Wireless) Performance

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