Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems. In this paper we propose the use of a multi-objective adaptive immune algorithm (M 2 AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch-and-bound multi-objective mapping algorithms. We tested algorithm on several SoC applications.
As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (quality of security service) to overcome present MPSoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. QoSS takes advantage of the NoC wide system visibility and critical role in enabling system operation, exploiting the NoC components to detect and prevent a wide range of attacks. In this paper, we present the implementation of a layered dynamic security NoC architecture that integrates agile and dynamic security firewalls in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of different security policies for several MPSoC applications.
MPSoCs have been proposed as a promising architecture choice to overcome the challenging embedded electronics requirements, characterized by tights development times and fast evolution of applications. The MPSoC flexibility, also represents a system vulnerability. As security requirements vary dramatically for different applications, the challenge is to provide MPSoC security that allows a trustworthy system that meets all the security requirements of such applications. NoC has become an attractive alternative to support the MPSoC communication requirements. Our work proposes the implementation of dynamic security architecture to overcome present MPSoC vulnerabilities. We integrate agile and dynamic security firewalls into the NoC in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications.
Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M 2 AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 wellknown benchmarks, including random and real applications, and combines up to 8 applications at the same SoC.The experimental results showed that the M 2 AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.
Network-on-chip (NoC) is becoming important as the communication structure of the MPSoC (Multi-processor-Systemon-Chip). Designing an optimal NoC for satisfying the MPSoC communication and security requirements involves the specification of a large set of configuration parameters. IP mapping is one of the most critical parameters in Network-onchip (NoC) design, strongly influencing the MPSoC performance. IP mapping has been solved using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (MAIAS), an evolutionary approach to solve the multi-application NoC mapping problem targeting security issues, while achieving the best performance. Our results are compared with those of the genetic and branch-and-bound multi-objective mapping algorithms. MAIAS obtained better results than PBBB and MGAP in a shorter time. The experimental results showed that the MAIAS achieves configurations that fulfill the security requirements while decreasing the power consumption in 26% and the latency in 41% compared to the branch-and-bound approach and 35% and 37% over the genetic approach.
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