Data synchronization issues in GALS SoCs

Abstract

Locally generated, arbitrated clocks for GALS SoCs [1] face the risk of synchronization failures if clock delays are not accounted for. The problem is analyzed based on clock delays, cycle times, and complexity of the asynchronous port controllers. A number of methods are presented. In some cases, it is sufficient to extract all the delays and verify whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, asynchronous synchronizers or matched-delay asynchronous ports may be employed. Arbitrated clocks may be traded off for locally delayed input and output ports, facilitating high data rates. The latter circuits have been simulated, to verify their performance.

Analysis and optimization of pausible clocking based GALS design

“…This method is only suitable for pipelined systems. Recent work in [12,19] reveals that, for clock delays satisfying Δ LClkRx < T LClkRx , there are two timing regions in each cycle of LClk Rx , as shown in Fig. 7 for example, where negligible synchronization failure probability can be expected [12].…”

“…An interface circuit using partial handshake signals was shown in [11] for high-speed systems with large clock delay, while there is an unknown nonzero probability of failure in the circuits. For the design of GALS systems insensitive to the clock tree delay, a synchronizing scheme based on locally delayed latching (LDL) was presented in [12,19]. Since the clocks can't be paused in the LDL interface, it introduces additional timing constraints on both the asynchronous input port controller and the combinational logic following the sampling register FF, which limits its application.…”

“…Another approach to GALS systems is the use of asynchronous FIFOs [2,3], and this results in overheads in both area and power. In recent years, an alternative method to GALS design, which is mainly based on pausible local clocks, has been developed [4,5,6,7,8,9,10,11,12]. Communication between asynchronous modules is achieved using a pair of request-acknowledge handshaking signals, and the local clocks are paused and stretched, if necessary, to avoid metastability in data transfer.…”

Carrier and Symbol Phase Synchronizers

“…Each one of the four synchronizers will be tested when the carrier input changes between sinusoidal wave, triangular wave and rectangular wave [10,11,12,13,14,15].…”

Interface Design for Rationally Clocked GALS Systems

“…The latter is usually achieved either by control signaling [10,1] or by temporarily stopping the sender's clock [12,6]. Unfortunately, solutions that involve stopping or stretching of clocks are not well-suited for high-speed designs with IP cores having large clock-buffer delays [6,4]. Consequently, practical designers often avoid this solution.…”