Interface Design for Rationally Clocked GALS Systems

Mekie, Joycee; Chakraborty, Supratik; Venkataramani, Girish; Thiagarajan, P. S.; Sharma, Dinesh K.

doi:10.1109/async.2006.19

Cited by 13 publications

(4 citation statements)

References 10 publications

(15 reference statements)

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“…While we have used path guards and anchor nodes to combine the constraints represented by sequence diagrams and those represented by ATDs, further research into alternative ways of specifying event sequences of interest is needed. Finally, it is worthwhile exploring other specification formalisms like delay-augmented net-charts [19] for describing sequencing and quantitative synchronization constraints, while still achieving a logical separation of the two specifications.…”

Section: Resultsmentioning

confidence: 99%

Reasoning about synchronization in GALS systems

Chakraborty

Mekie

Sharma

2006

Form Method Syst Des

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Correct design of interface circuits is crucial for the development of System-onChips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.

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Section: Resultsmentioning

confidence: 99%

Reasoning about synchronization in GALS systems

Chakraborty

Mekie

Sharma

2006

Form Method Syst Des

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“…Sarmenta's solution cannot tolerate an unknown skew between the clocks and therefore cannot be used without a globally-balanced clock tree. There has been a recent extension of Sarmenta's approach [20], which argues that Rational Clocking is essentially a worstcase technique and proposes a formalism, delay-augmented netcharts, for the optimization of the synchronization interfaces. This approach improves performances but shares the same limitations of the Rational Clocking approach as it also requires a known phase difference between the clocks.…”

Section: Related Workmentioning

confidence: 99%

Lowering the latency of interfaces for rationally-related frequencies

Chabloz

Hemani

2010

2010 IEEE International Conference on Computer Design

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We have introduced the Globally-Ratiochronous, Locally-Synchronous (GRLS) design paradigm, a design style based on rationally-related frequencies, with the objective to overcome the limitations of traditional multi-frequency systems by providing a flexibility close that of Globally-Asynchronous, Locally-Synchronous (GALS) systems but introducing performance penalties and overheads close to those of mesochronous systems. In this paper we focus on performances and improve the latency figures of our original GRLS interfaces by introducing two new interfaces, called GRLS-F and GRLS-noF, the first suitable for blocks with long computation time and the second for blocks with short computation time. The latency figures of the original GRLS interfaces are improved up to 50% without increasing complexity. The average latency figures of the resulting interfaces are lower than 1 Receiver clock cycle, the latency of a synchronous interface.

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“…various clock domains has been also evaluated [9]. Applying clock signals with different frequencies is experimented in some researches, while the frequencies are the factor of a constant integer [10,11]. Most of the suggested remedies are time dependent, making them useless in global synchronization approaches.…”

Section: Introductionmentioning

confidence: 99%

A GALS Router for Asynchronous Network-on-Chip

Yaghini

Bagherzadeh

2014

Proceedings of International Workshop on Manycore Embedded Systems

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A scalable asynchronous NoC router with lower power consumption and latency comparing to a synchronous design is introduced in this article. It employs GALS interfaces (synchronous to asynchronous/asynchronous to synchronous), imposing negligible area overhead to handle the Metastability issue. It is synthesized with the help of Persia tool, resulting in 23165 transistors. The power consumption and delay factor have been evaluated by means of H-Spice toolset in 90nm manufacturing technology. According to the experimental results the proposed asynchronous design consumes less power than synchronous scheme by removing clock signals. The imposed area overhead of asynchronous design is reported 36% higher than synchronous one.

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Interface Design for Rationally Clocked GALS Systems

Abstract: We

Cited by 13 publications

References 10 publications

Reasoning about synchronization in GALS systems

Reasoning about synchronization in GALS systems

Lowering the latency of interfaces for rationally-related frequencies

A GALS Router for Asynchronous Network-on-Chip

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