Reasoning about synchronization in GALS systems

Abstract

Correct design of interface circuits is crucial for the development of System-onChips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.

High Rate Data Synchronization in GALS SoCs

“…In [20], abstract timing diagrams are used for analyzing synchronization interfaces, instead of the signal transition graph (STG) analysis [21] employed in [15]. In addition, [20] and [22] propose a new interfacing scheme, with a pausable clock generator at the transmitter side and free-running clock and partial handshake on the receiver side.…”

“…In addition, [20] and [22] propose a new interfacing scheme, with a pausable clock generator at the transmitter side and free-running clock and partial handshake on the receiver side. Unfortunately, the authors report in [20] that without a biased MUTEX (a MUTEX that prioritizes one of the inputs, which is in practice physically unrealizable) the scheme may lead to "erroneous communication and loss of messages" when the communicating modules are not perfectly synchronized (in terms of data throughput). Reference [20] proposes a FIFO to partially solve that problem, whereby the clock is paused on the transmitter side when the FIFO is full.…”

“…Unfortunately, the authors report in [20] that without a biased MUTEX (a MUTEX that prioritizes one of the inputs, which is in practice physically unrealizable) the scheme may lead to "erroneous communication and loss of messages" when the communicating modules are not perfectly synchronized (in terms of data throughput). Reference [20] proposes a FIFO to partially solve that problem, whereby the clock is paused on the transmitter side when the FIFO is full. A detailed circuit at the transistor-level is presented in [22].…”

“…19 simplifies the input port of Section VI-F, eliminating the asynchronous controller from the input port. The input port delay now depends on the external delays of the output port (20) The matched delay in Fig. 19 could have been reduced from to , but when is unknown a priori, it is better to leave the matched delay at .…”

Asynchronous on-chip networks

“…Chakraborty et al in [17] discuss using abstract timing diagrams to reason about the correctness of interfacing techniques between synchronous modules. They point out that there are various different interfacing techniques available but it is difficult to compare them due to differences of analysis carried out for each of them.…”