High Rate Data Synchronization in GALS SoCs

Abstract

Abstract-Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner.

Metastability Tolerant Computing

“…for plesiosynchronous, rationally-related, and periodic clocks [8]- [10], or (ii) explores time-unbounded decision schemes such as pausible/stretchable clocking [11]- [13]. Few proposed "speculative" synchronization schemes do not target the clocking process itself as such but focus on overlapping synchronization with computation using architectural techniques [7], [14], [15].…”

Asynchronous Current Mode Serial Communication

“…1) employs low-latency synchronizers at the source and sink [44], two-phase NRZ level encoded dual rail (LEDR) data/strobe (DS) encoding [45]- [47] and an asynchronous handshake protocol (allowing non-uniform delay intervals between successive bits), serializer and de-serializer and line drivers and receivers. Acknowledgment is returned only once per word, rather than bit by bit, enabling multiple bits in a wave-pipelined manner over the serial channel.…”

Measurements of metastability in MUTEX on an FPGA

“…However, the modern SoCs built in deep process technology nodes face some challenges. The increase of wire delays, process, temperature, voltage (PVT) variations make timing closures become difficult issues that take much time and efforts of SoCs' designers in design and verification [1,2]. Particularly, it is more difficult to distribute a huge global clock network over entire chip with low clock skews.…”

“…Furthermore, the power/energy consumption can be saved when each locally synchronous module works with its optimal clock frequency [2]. Since different modules use unrelated clock frequencies, such a system can be called a globally asynchronous locally synchronous (GALS) system [1]. Another benefit of the GALS system is the electromagnetic inference (EMI) can be reduced since their locally synchronous modules operate either at different frequencies or at different phases [3,4].…”