Advanced passive devices for enhanced integrated RF circuit performance

Coolbaugh, D.; Eshun, E.; Groves, R.; Hararnel, D.; Johnson, J. B.; Harnmad, A.; He, Z.X.; Vidhya, R.; Stein, K. U.; Ongel, S. St; Subbanna, S.; Wang, D.; Volant, R.; Wang, X.; Watson, K.

doi:10.1109/rfic.2002.1012063

Cited by 28 publications

(5 citation statements)

References 1 publication

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“…On-chip capacitor specifications include capacitance density, voltage linearity, leakage current, mismatch, and Q-factor [1]. It has not been trivial to achieve both high Q-factor and capacitance density, and either of the two has been optimized at the expense of the other [2]- [4]. As semiconductor technology develops, the minimum definable feature size decreases, and the number of layers increases.…”

Section: Symmetric Vertical Parallel Plate Capacitors Formentioning

confidence: 99%

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

Kim

Plouchart

et al. 2007

IEEE Electron Device Lett.

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This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and Q-factor. An effective capacitance of 2.18 fF/µm 2 and a Q-factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configuration's pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed. Index Terms-Radio frequency (RF) passive component, vertical and horizontal scalability, vertical native back-end-of-line (BEOL) capacitor, vertical parallel plate (VPP) capacitor, 65-nm silicon-on-insulator (SOI) CMOS technology.

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Section: Symmetric Vertical Parallel Plate Capacitors Formentioning

confidence: 99%

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

Kim

Plouchart

et al. 2007

IEEE Electron Device Lett.

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“…To achieve a higher capacitance per unit area for providing the analog scaling is the main objective. Since capacitance is a direct function of the dielectric constant of the insulator, the replacement of currently used silicon oxide or silicon nitride films with the new alternative dielectrics which have higher permittivity values is a very promising approach (1,2).…”

Section: Introductionmentioning

confidence: 99%

Alternative High-k Dielectrics for Metal-Insulator-Metal Applications

Lukosius¹,

Kaynak²,

Wenger³

et al. 2010

ECS Trans.

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Atomic Vapor Deposition (AVD) technique was successfully applied for the depositions of amorphous HfO 2 , Sr-Ta-O and Ti-Ta-O thin films, which were investigated as alternative dielectrics to replace the standard SiO 2 or Si 3 N 4 dielectrics used in Metal-Insulator-Insulator (MIM) capacitors. Metal oxides were grown on 200 mm TiN/Si (100) substrates within the thermal budget of back-end-of-line (BEOL) process. Electrical properties, investigated after sputtering Au top electrodes, revealed that the main characteristics are different for each dielectric. On one hand, Ti-Ta-O based MIM capacitors possessed a dielectric constant of 50, which is more than a factor of 2 higher compared to the ones of Sr-Ta-O (20) and HfO 2 (18). On the other hand, Sr-Ta-O based MIM capacitors showed the lowest leakage current densities as well as the smallest capacitance-voltage linearity coefficients.

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“…In recent times, ultra-fast silicon bipolar transistors using silicongermanium technology have been demonstrated at operating frequencies as high as 375 GHz [1]. Passive components, for instance, resistors, capacitors and inductors, also play a significant role in the current wireless communication revolution [2]. The operation of RF circuits is, hence more prone to the quality and performance of passive elements.…”

Section: Introductionmentioning

confidence: 99%

High-performance thick copper inductors in an RF technology

Vaed

Graham

Steen

et al. 2004

Micromachining and Microfabrication Process Technology IX

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With the emergence of wired and wireless communication technologies, on-chip inductors find applications in a variety of high performance radio frequency (RF) circuits. In this work, we present two approaches for high-performance copper inductors in an RF technology. In the first approach (Type I), we lower ohmic losses to realize a high Q-factor. This is achieved by using, for the first time in a manufacturable technology, 4 µm thick copper spirals along with a 4 µm thick copper underpass on high-resistivity substrates (75 Ω-cm). The underpass is connected to the spirals with a 4 µm tall copper via, which lowers spiral to underpass capacitance. For further lowering the capacitive losses, an additional 6.1 µm thick interlayer dielectric separates the underpass from the substrate. In the second approach (Type II), we utilize a novel one-mask CMOS-compatible micromachining scheme to eliminate substrate losses. This is achieved by completely removing the silicon substrate from directly below the inductors. For a 1.1nH inductor, peak-Q shows an impressive two-fold improvement from 26.6 at 3.8 GHz for Type I inductor to 52.8 at 8.2 GHz for Type II inductor after silicon micromachining. The resonant frequency increases from 18 GHz to 27 GHz after substrate micromachining.

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Advanced passive devices for enhanced integrated RF circuit performance

Cited by 28 publications

References 1 publication

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

Alternative High-k Dielectrics for Metal-Insulator-Metal Applications

High-performance thick copper inductors in an RF technology

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