Integration of graphene with Si microelectronics is very appealing by offering a potentially broad range of new functionalities. New materials to be integrated with the Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etching and electrochemical delamination methods with respect to residual submonolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection X-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10(13) atoms/cm(2). These metal impurities appear to be partially mobile upon thermal treatment, as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics, these results reveal that further progress in synthesis, handling, and cleaning of graphene is required to advance electronic and optoelectronic applications.

Training and recognition with neural networks generally require high throughput, high energy efficiency, and scalable circuits to enable artificial intelligence tasks to be operated at the edge, i.e., in battery-powered portable devices and other limited-energy environments. In this scenario, scalable resistive memories have been proposed as artificial synapses thanks to their scalability, reconfigurability, and high-energy efficiency, and thanks to the ability to perform analog computation by physical laws in hardware. In this work, we study the material, device, and architecture aspects of resistive switching memory (RRAM) devices for implementing a 2-layer neural network for pattern recognition. First, various RRAM processes are screened in view of the device window, analog storage, and reliability. Then, synaptic weights are stored with 5-level precision in a 4 kbit array of RRAM devices to classify the Modified National Institute of Standards and Technology (MNIST) dataset. Finally, classification performance of a 2-layer neural network is tested before and after an annealing experiment by using experimental values of conductance stored into the array, and a simulation-based analysis of inference accuracy for arrays of increasing size is presented. Our work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption.

We report on the resistive switching in TiN/Ti/HfO/TiN memristive devices. A resistive switching model for the device is proposed, taking into account important experimental and theoretical findings. The proposed switching model is validated using 2D and 3D kinetic Monte Carlo simulation models. The models are consistently coupled to the electric field and different current transport mechanisms such as direct tunneling, trap-assisted tunneling, ohmic transport, and transport through a quantum point contact have been considered. We find that the numerical results are in excellent agreement with experimentally obtained data. Important device parameters, which are difficult or impossible to measure in experiments, are calculated. This includes the shape of the conductive filament, width of filament constriction, current density, and temperature distribution. To obtain insights in the operation of the device, consecutive cycles have been simulated. Furthermore, the switching kinetics for the forming and set process for different applied voltages is investigated. Finally, the influence of an annealing process on the filament growth, especially on the filament growth direction, is discussed.